74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset
February 1992
Revised June 2001
74LVQ174
Low Voltage Hex D-Type Flip-Flop with Master Reset
General Description
The LVQ174 is a high-speed hex D-type flip-flop. The
device is used primarily as a 6-bit edge-triggered storage
register. The information on the D inputs is transferred to
storage during the LOW-to-HIGH clock transition. The
device has a Master Reset to simultaneously clear all flip-
flops.
Features
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Guaranteed incident wave switching into 75
Ω
Ordering Code:
Order Number
74LVQ174SC
74LVQ174SJ
Package Number
M16A
M16D
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
5
CP
MR
Q
0
–Q
5
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
© 2001 Fairchild Semiconductor Corporation
DS011353
www.fairchildsemi.com
74LVQ174
Functional Description
The LVQ174 consists of six edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops. Each D
input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A
LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The LVQ174 is
useful for applications where the true output only is
required and the Clock and Master Reset are common to
all storage elements.
Truth Table
Inputs
MR
L
H
H
H
CP
D
X
H
L
X
Output
Q
L
H
L
Q
X
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74LVQ174
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
(I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or
Sink Current
−
0.5V to
+
7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
200 mA
−
65
°
C to
+
150
°
C
±
100 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
V/
∆
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 3.0V
125 mV/ns
2.0V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
V
OL
Maximum Low Level
Output Voltage
I
IN
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input
Leakage Current
Minimum Dynamic (Note 4)
Output Current
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
V
CC
(V)
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.3
3.3
3.3
3.3
0.7
−0.6
1.8
1.6
4.0
0.8
−0.8
2.0
0.8
0.002
T
A
= +25°C
Typ
1.5
1.5
2.99
2.0
0.8
2.9
2.58
0.1
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
0.8
2.9
2.48
0.1
0.44
±1.0
36
−25
40.0
V
V
V
V
V
V
µA
mA
mA
µA
V
V
V
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
(Note 3)
I
OH
= −12
mA
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
(Note 3)
I
OL
=
12 mA
V
I
=
V
CC
,
GND
V
OLD
=
0.8V Max (Note 5)
V
OHD
=
2.0V Min (Note 5)
V
IN
=
V
CC
or GND
(Note 6)(Note 7)
(Note 6)(Note 7)
(Note 6)(Note 8)
(Note 6)(Note 8)
Units
Conditions
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed.
Note 6:
Worst case package.
Note 7:
Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8:
Max number of Data Inputs (n) switching. (n
−
1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f
=
1 MHz.
3
www.fairchildsemi.com
74LVQ174
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
V
CC
(V)
f
MAX
t
PLH
t
PHL
t
PHL
t
OSHL
,
t
OSLH
Maximum Clock
Frequency
Propagation Delay
CP to Q
n
Propagation Delay
CP to Q
n
Propagation Delay
MR to Q
n
Output to
Output Skew (Note 9)
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
Min
60
90
2.0
2.0
2.0
2.0
2.5
2.5
C
L
=
50 pF
Typ
90
100
10.8
9.0
10.2
8.5
10.8
9.0
1.0
1.0
16.2
11.5
15.5
11.0
16.2
11.5
1.5
1.5
Max
50
70
1.5
1.5
1.5
1.5
2.0
2.0
18.0
12.5
17.0
12.0
18.0
12.5
1.5
1.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
Max
MHz
ns
ns
ns
ns
Units
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
(V)
t
S
t
H
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
t
W
t
W
t
REC
MR Pulse Width, LOW
CP Pulse Width
Recovery Time
MR to CP
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
2.7
3.3
±
0.3
Typ
3.0
2.5
1.2
1.0
1.2
1.0
1.2
1.0
0
0
C
L
=
50 pF
8.0
6.5
4.0
3.0
7.0
5.5
7.0
5.5
3.5
2.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
10.0
7.0
4.5
3.0
10.0
7.0
10.0
7.0
3.5
2.5
ns
ns
Units
ns
ns
ns
Capacitance
Symbol
C
IN
C
PD
(Note 10)
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
23
Units
pF
pF
V
CC
=
Open
V
CC
=
3.3V
Conditions
Note 10:
C
PD
is measured at 10 MHz.
www.fairchildsemi.com
4
74LVQ174
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
www.fairchildsemi.com
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
