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74LCX16646 Low Voltage 16-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs
February 1994
Revised August 2002
74LCX16646
Low Voltage 16-Bit Transceiver/Register
with 5V Tolerant Inputs and Outputs
General Description
The LCX16646 contains sixteen non-inverting bidirectional
registered bus transceivers with 3-STATE outputs, provid-
ing multiplexed transmission of data directly from the input
bus or from the internal storage registers. Each byte has
separate control inputs which can be shorted together for
full 16-bit operation.The DIR inputs determine the direction
of data flow through the device. The CPAB and CPBA
inputs load data into the registers on the LOW-to-HIGH
transition (see Functional Description).
The LCX16646 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX16646 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V–3.6V V
CC
specifications provided
s
5.2 ns t
PD
max (V
CC
=
3.3V), 20
µ
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
±
24 mA Output Drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human Body Model
>
2000V
Machine Model
>
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX16646MEA
74LCX16646MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and
#2 control pins.
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2
74LCX16646
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74LCX16646
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both. The select (SAB
n
, SBA
n
) controls can multiplex
stored and real-time. The examples shown below demon-
strate the four fundamental bus-management functions
that can be performed.
The direction control (DIR
n
) determines which bus will
receive data when OE
n
is LOW. In the isolation mode (OE
n
HIGH), A data may be stored in one register and/or B data
may be stored in the other register. When an output func-
tion is disabled, the input function is still enabled and may
be used to store and transmit data. Only one of the two
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