74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
October 2001
Revised October 2001
74ALVC16821
Low Voltage 20-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16821 contains twenty non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications.
The 74ALVC16821 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16821 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V–3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
4.0 ns max for 3.0V to 3.6V V
CC
4.9 ns max for 2.3V to 2.7V V
CC
8.8 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC16821MTD
Package Number
MTD56
Package Descriptions
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
CLK
n
D
0
–D
19
O
0
–O
19
Description
Output Enable Input (Active LOW)
Clock Input
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation
DS500685
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74ALVC16821
Connection Diagram
Truth Tables
Inputs
CLK
1
OE
1
H
L
L
L
Inputs
CLK
2
OE
2
H
L
L
L
D
10
–D
19
X
L
H
X
D
0
–D
9
X
L
H
X
Outputs
O
0
–O
9
Z
L
H
O
0
Outputs
O
10
–O
19
Z
L
H
O
0
L or H
X
L or H
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
O
0
=
Previous O
0
before LOW-to-HIGH transition of Clock
=
LOW-to-HIGH transition
Functional Description
The 74ALVC16821 contains twenty D-type flip-flops with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
each other. Control pins can be shorted together to obtain
full 20-bit operation. The following description applies to
each byte. The twenty flip-flops will store the state of their
individual D-type inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CLK) transition.
The 3-STATE standard outputs are controlled by the Out-
put Enable (OE
n
) input. When OE
n
is HIGH, the standard
outputs are in the high impedance mode but this does not
interfere with entering new data into the flip-flops.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ALVC16821
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 3)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 4)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 2:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
=
100
µA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −12
mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
12 mA
I
OL
=
24 mA
I
I
I
OZ
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
3.6
3.6
3.6
3 - 3.6
V
CC
- 0.2
1.2
2.0
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5.0
±10
40
750
µA
µA
µA
µA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
3
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74ALVC16821
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
C
L
=
50 pF
V
CC
=
3.3V
±
0.3V
Min
f
MAX
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
W
t
S
t
H
Maximum Clock Frequency
Propagation Delay
CLK to O
n
Output Enable Time
Output Disable Time
Pulse Width
Setup Time
Hold Time
250
1.3
1.3
1.3
1.5
1.5
1.0
4.0
4.2
4.2
Max
V
CC
=
2.7V
Min
200
1.5
1.5
1.5
1.5
1.5
1.0
4.9
5.3
4.7
Max
C
L
=
30 pF
V
CC
=
2.5V
±
0.2V
Min
200
1.0
1.0
1.0
1.5
1.5
1.0
4.4
4.7
4.2
Max
V
CC
=
1.8V
±
0.15V
Min
100
1.5
1.5
1.5
4.0
2.5
1.0
8.8
9.8
7.6
Max
MHz
ns
ns
ns
ns
ns
ns
Units
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
Conditions
V
I
=
0V or V
CC
V
I
=
0V or V
CC
Outputs Enabled f
=
10 MHz, C
L
=
50 pF
T
A
= +25°C
V
CC
3.3
3.3
3.3
2.5
Typical
6
7
20
20
pF
pF
pF
Units
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4
74ALVC16821
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
SWITCH
Open
V
L
GND
FIGURE 1. AC Test Circuit
TABLE 2.
Symbol
V
mi
V
mo
V
X
V
Y
V
L
V
CC
3.3V
±
0.3V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.7V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.5V
±
0.2V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
1.8V
±
0.15V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
FIGURE 2. Waveform for Inverting
and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable
and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable
and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width
and t
rec
Waveforms
FIGURE 6. Setup Time, Hold Time
and Recovery Time for Low Voltage Logic
5
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