74ACQ657 • 74ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and
3-STATE Outputs
January 1990
Revised September 2000
74ACQ657 • 74ACTQ657
Quiet Series
Octal Bidirectional Transceiver with
8-Bit Parity Generator/Checker and 3-STATE Outputs
General Description
The ACQ/ACTQ657 contains eight non-inverting buffers
with 3-STATE outputs and an 8-bit parity generator/
checker. Intended for bus oriented applications, the device
combines the 245 and the 280 functions in one package.
The ACQ/ACTQ utilizes Fairchild Quiet Series
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO
output control and undershoot corrector in
addition to a split ground bus or superior performance.
Features
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Combines the 245 and the 280 functions in one package
s
300 mil 24-pin slim dual-in-line package
s
Outputs source/sink 24 mA
s
ACTQ has TTL-compatible inputs
Ordering Code:
Order Number
74ACQ657SPC
74ACTQ657SC
74ACTQ657SPC
Package Number
N24C
M24B
N24C
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
0
–A
7
B
0
–B
7
T/R
OE
PARITY
ODD/EVEN
ERROR
Description
Data Inputs/3-STATE Outputs
Data Inputs/3-STATE Outputs
Transmit/Receive Input
Enable Input
Parity Input/3-STATE Output
ODD/EVEN Parity Input
Error 3-STATE Output
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010636
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74ACQ657 • 74ACTQ657
Functional Description
The Transmit/Receive (T/R) input determines the direction
of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from the A-Port to the
B-Port; Receive (active LOW) enables data from the B-Port
to the A-Port.
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B Ports by placing
them in a HIGH-Z condition when the Output Enable input
is HIGH.
When transmitting (T/R HIGH), the parity generator detects
whether an even or odd number of bits on the A-Port are
HIGH and compares these with the condition of the parity
select (ODD/EVEN). If the Parity Select is HIGH and an
even number of A inputs are HIGH, the Parity output is
HIGH.
In receiving mode (T/R LOW), the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input. If an even number of bits on the B-Port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR will be HIGH to indicate no error. If an
odd number of bits on the B-Port are HIGH, the parity
select is HIGH, and the PARITY input is HIGH, the ERROR
will be LOW indicating an error.
Function Table
Number of
Inputs That
Are High
0, 2, 4, 6, 8
OE
L
L
L
L
L
L
1, 3, 5, 7
L
L
L
L
L
L
Immaterial
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Inputs
T/R
H
H
L
L
L
L
H
H
L
L
L
L
X
ODD/EVEN
H
L
H
H
L
L
H
L
H
H
L
L
X
Input/
Output
Parity
H
L
H
L
H
L
L
H
H
L
H
L
Z
Outputs
ERROR
Z
Z
H
L
L
H
Z
Z
L
H
H
L
Z
Outputs Mode
Transmit
Transmit
Receive
Receive
Receive
Receive
Transmit
Transmit
Receive
Receive
Receive
Receive
Z
H
Function Table
Inputs
Outputs
OE
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
T/R
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
High-Z State
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2
74ACQ657 • 74ACTQ657
Functional Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74ACQ657 • 74ACTQ657
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-up Source
Sink Current
Junction Temperature (T
J
)
PDIP
140
°
C
−
0.5V to
+
7.0V
−
20 MA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
50 mA
−
65
°
C to
+
150
°
C
±
300 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
ACQ
ACTQ
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆
V/
∆
t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@3.0V, 4.5V, 5.5V
Minimum Input Edge Rate
∆
V/
∆
t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@4.5V, 5.5V
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
125 mV/ns
DC Electrical Characteristics for ACQ
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Voltage Output
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 4)
I
OLD
I
OHD
I
OZT
Maximum Input Leakage Current
(T/R, OE, ODD/EVEN Inputs)
Minimum Dynamic
Output Current (Note 3)
Maximum I/O Leakage Current
(A
n
, B
n
Inputs)
V
OLP
Quiet Output Maximum
Dynamic V
OL
5.5
±0.6
±6.0
µA
5.5
5.5
5.5
5.5
8.0
0.002
0.001
0.001
T
A
= +25°C
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.85
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
V
IN
=
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
IN
=
V
IL
or V
IH
0.44
0.44
0.44
±1.0
75
−75
80.0
µA
mA
mA
µA
V
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
5.0
1.1
1.5
V
Figures 1, 2
(Note 5)(Note 6)
V
I
OUT
=
50
µA
V
I
OH
= −12
mA
I
OH
= −24mA
I
OH
= −24
mA (Note 2)
V
I
OUT
= −50 µA
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
Units
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
I
CC
(Note 4) Maximum Quiescent Supply Current
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4
74ACQ657 • 74ACTQ657
DC Electrical Characteristics for ACQ
Symbol
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level Dynamic
Input Voltage
Maximum LOW Level Dynamic
Input Voltage
V
CC
(V)
5.0
5.0
5.0
Typ
−0.6
3.1
1.9
(Continued)
T
A
= −40°C
to
+85°C
Guaranteed Limits
−1.2
3.5
1.5
V
V
V
Figures 1, 2
(Note 5)(Note 6)
(Note 5)(Note 7)
(Note 5)(Note 7)
T
A
= +25°C
Units
Conditions
Note 2:
Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 5:
DIP package.
Note 6:
Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7:
Max number of Data Inputs (n) switching. (n−1) Inputs switching 0V to 5V (ACQ).Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
) f
=
1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZT
I
CCT
I
OLD
I
OHD
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input Leakage Current
(T/R, OE, ODD/EVEN Inputs)
Maximum I/O Leakage Current
(A
n
, B
n
Inputs)
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 9)
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
1.2
8.0
1.5
−1.2
2.2
0.8
0.6
1.5
75
−75
80.0
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
±0.6
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±6.0
µA
µA
mA
mA
mA
µA
V
V
V
V
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24mA
I
OH
= −24
mA (Note 8)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 8)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figures 1, 2
(Note 10)(Note 11)
Figures 1, 2
(Note 10)(Note 11)
(Note 10)(Note 12)
(Note 10)(Note 12)
I
CC
(Note 4) Maximum Quiescent Supply Current
Note 8:
All outputs loaded; thresholds on input associated with output under test.
Note 9:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 10:
DIP package.
Note 11:
Max number of outputs defined as (n). n−1 Data Inputs are driven 0V to 3V; one output @ GND.
Note 12:
Max number of Data Inputs (n) switching. (n−1) Inputs switching 0V to 3V (ACQ). Input-under-test switching; 3V to threshold (V
ILD
),
0V to threshold (V
IHD
) f
=1
MHz.
5
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