74ACT16373 16-Bit Transparent Latch with 3-STATE Outputs
August 1999
Revised May 2005
74ACT16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACT16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is low, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state.
Features
s
Separate control logic for each byte
s
16-bit version of the ACT373
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT16373SSC
74ACT16373MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
LE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active Low)
Latch Enable Input
Inputs
Outputs
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500297
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74ACT16373
Functional Description
The ACT16373 contains sixteen D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the D
n
enters the latches. In this condition the latches are
transparent, i.e., a latch output will change states each time
its D input changes. When LE
n
is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE
n
. The
3-STATE standard outputs are controlled by the Output
Enable (OE
n
) input. When OE
n
is LOW, the standard out-
puts are in the 2-state mode. When OE
n
is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Truth Tables
Inputs
LE
1
X
H
H
L
OE
1
H
L
L
L
Inputs
LE
2
X
H
H
L
OE
2
H
L
L
L
I
8
–I
15
X
L
H
X
I
0
–I
7
X
L
H
X
Outputs
O
0
–O
7
Z
L
H
(Previous)
Outputs
O
8
–O
15
Z
L
H
(Previous)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Previous previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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2
74ACT16373
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
V
O
V
O
0.5V to
7.0V
20 mA
20 mA
20 mA
20 mA
0.5V to V
CC
0.5V
50 mA
50 mA
140
q
C
65
q
C to
150
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
0.5V
V
CC
0.5V
0.5V
V
CC
0.5V
DC Output Diode Current (I
OK
)
40
q
C to
85
q
C
125 mV/ns
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin
Junction Temperature
Storage Temperature
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
Maximum 3-STATE
Leakage Current
Maximum Input
Leakage Current
Maximum I
CC
/Input
Max Quiescent Supply Current
Minimum Dynamic
Output Current (Note 3)
5.5
5.5
5.5
5.5
5.5
0.6
8.0
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Units
V
OUT
V
OUT
Conditions
0.1V
0.1V
Guaranteed Limits
V
V
V
or V
CC
0.1V
or V
CC
0.1V
I
OUT
V
IN
V
I
OH
I
OH
V
I
OUT
V
IN
V
I
OL
I
OL
V
I
V
O
V
I
V
I
V
IN
V
OLD
V
OHD
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 2)
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 2)
V
IL
, V
IH
V
CC
, GND
V
CC
, GND
V
CC
2.1V
V
CC
or GND
1.65V Max
3.85V Min
r
0.5
r
0.1
r
5.0
r
1.0
1.5
80.0
75
P
A
P
A
mA
P
A
mA
mA
75
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms; one output loaded at a time.
3
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74ACT16373
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable
Delay
Output Disable
Delay
5.0
5.0
5.0
(V)
(Note 4)
5.0
Min
3.1
2.6
3.1
2.8
2.5
2.7
2.1
2.0
T
A
C
L
25
q
C
50 pF
Typ
5.3
4.6
5.4
4.9
4.7
4.8
5.1
4.5
Max
7.9
7.3
7.9
7.3
7.4
7.5
7.9
7.4
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
8.4
7.8
8.4
7.8
7.9
8.0
8.2
7.9
ns
ns
ns
ns
Units
Min
3.1
2.6
3.2
2.8
2.5
2.7
2.1
2.0
Note 4:
Voltage Range 5.0 is 5.0V
r
0.5V.
AC Operating Requirements
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or
LOW, Input to Clock
Hold time, HIGH or
LOW, Input to Clock
CS Pulse Width,
HIGH or LOW
Note 5:
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
(V)
(Note 5)
5.0
5.0
5.0
Guaranteed Minimum
3.0
1.5
4.0
3.0
1.5
4.0
ns
ns
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
30
Units
pF
pF
V
CC
V
CC
5.0V
5.0V
Conditions
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4
74ACT16373
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
5
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