74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
August 1999
Revised October 1999
74ACT16240
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACT16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
Features
s
Separate control logic for each byte
s
16-bit version of the ACT240
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT16240SSC
74ACT16240MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Inputs (Active LOW)
Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500293
www.fairchildsemi.com
74ACT16240
Truth Tables
Inputs
OE
1
L
L
H
I
0
–I
3
L
H
X
Outputs
O
0
–O
3
H
L
Z
OE
2
L
L
H
Inputs
I
4
–I
7
L
H
X
Outputs
O
4
–O
7
H
L
Z
Inputs
OE
3
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Outputs
I
8
–I
11
L
H
X
O
8
–O
11
H
L
Z
OE
4
L
L
H
Inputs
I
12
–I
15
L
H
X
Outputs
O
12
–O
15
H
L
Z
Functional Description
The ACT16240 contains sixteen inverting buffers with 3-
STATE standard outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dently of the other. The control pins may be shorted
together to obtain full 16-bit operation. The 3-STATE out-
puts are controlled by an Output Enable (OE
n
) input for
each nibble. When OE
n
is LOW, the outputs are in 2-state
mode. When OE
n
is HIGH, the outputs are in the high
impedance mode, but this does not interfere with entering
new data into the inputs.
Logic Diagram
www.fairchildsemi.com
2
74ACT16240
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin
Junction Temperature
Storage Temperature
±
50 mA
+140°C
−65°C
to
+150°C
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
±
50 mA
−20
mA
+20
mA
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT™ circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Max Quiescent Supply Current
Minimum Dynamic
Output Current (Note 3)
5.5
5.5
5.5
5.5
5.5
0.6
8.0
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.5
±
0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±5.0
±
1.0
1.5
80.0
75
−75
µA
µA
mA
µA
mA
mA
V
V
V
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
IN
=
V
CC
or GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
Units
Conditions
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms; one output loaded at a time.
3
www.fairchildsemi.com
74ACT16240
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V.
T
A
= +25°C
C
L
=
50 pF
Min
2.7
3.0
2.5
2.7
2.3
2.0
Typ
4.8
5.1
4.5
4.7
5.0
4.6
Max
7.3
7.3
7.4
7.5
7.9
7.4
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
2.7
3.0
2.5
2.7
2.3
2.0
Max
7.8
7.8
7.9
8.0
8.2
7.9
ns
ns
ns
Units
Parameter
Propagation Delay
Data to Output
Output Enable Time
Output Disable Time
(V)
(Note 4)
5.0
5.0
5.0
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ
4.5
30
Units
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
Conditions
www.fairchildsemi.com
4
74ACT16240
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
5
www.fairchildsemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
