The ABT543 contains two sets of D-type latches, with sep-
arate input and output controls for each. For data flow from
A to B, for example, the A to B Enable (CEAB) input must
be low in order to enter data from the A Port or take data
from the B Port as indicated in the Data I/O Control Table.
With CEAB low, a low signal on (LEAB) input makes the A
to B latches transparent; a subsequent low to high transi-
tion of the LEAB line puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both low, the B output buffers are
active and reflect the data present on the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA.
Data I/O Control Table
Inputs
CEAB LEAB OEAB
H
X
L
X
L
X
H
L
X
X
X
X
X
H
L
Latched
Latched
Transparent
—
—
HIGH Z
—
—
HIGH Z
Driving
Latch Status
Output Buffers
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
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2
74ABT543
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disable or Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to
+5.5V
−0.5V
to V
CC
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500
mA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (∆V/∆t)
Data Input
Enable Input
Clock Input
50 mV/ns
20 mV/ns
100 mV/ns
−40°C
to
+85°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
V
ID
I
IH
I
BVI
I
BVIT
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Test
Input HIGH Current
Input HIGH Current Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
−1
−1
I
IH
+
I
OZH
Output Leakage Current
I
IL
+
I
OZL
Output Leakage Current
I
OS
I
CEX
I
ZZ
I
CCLH
I
CCL
I
CCZ
I
CCT
I
CCD
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Dynamic I
CC
(Note 5)
No Load
0.18
mA/MHz
Max
−100
10
−10
−275
50
100
50
30
50
2.5
µA
µA
mA
µA
µA
µA
mA
µA
mA
µA
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 3)
V
IN
=
0.0V (Non-I/O Pins)
0V–5.5V V
OUT
=
2.7V (A
n
, B
n
);
OEAB or CEAB
=
2V
0V–5.5V V
OUT
=
0.5V (A
n
, B
n
);
OEAB or CEAB
=
2V
Max
Max
0.0V
Max
Max
Max
Max
V
OUT
=
0V (A
n
, B
n
)
V
OUT
=
V
CC
(A
n
, B
n
)
V
OUT
=
5.5V (A
n
, B
n
);
All Others GND
All Outputs HIGH
All Outputs LOW
Outputs 3-STATE
All Others at V
CC
or GND
V
I
=
V
CC
−
2.1V
All Others at V
CC
or GND
Outputs Open, CEAB
and OEAB
=
GND, CEBA
=
V
CC
, One Bit Toggling,
50% Duty Cycle, (Note 4)
Note 3:
Guaranteed but not tested.
Note 4:
For 8-bit toggling. I
CCD
<
1.4 mA/MHz.
Note 5:
Guaranteed, but not tested.
Min
2.0
0.8
Typ
Max
Units
V
V
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18
mA (Non I/O Pins)
I
OH
= −3
mA, (A
n
, B
n
)
I
OH
= −32
mA, (A
n
, B
n
)
−1.2
2.5
2.0
0.55
4.75
1
1
7
100
V
V
V
µA
µA
µA
Min
0.0
Max
Max
Max
I
OL
=
64 mA, (A
n
, B
n
)
I
ID
=
1.9
µA,
(Non-I/O Pins)
All Other Pins Grounded
V
IN
=
2.7V (Non-I/O Pins) (Note 3)
V
IN
=
V
CC
(Non-I/O Pins)
V
IN
=
7.0V (Non-I/O Pins)
V
IN
=
5.5V (A
n
, B
n
)
3
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74ABT543
DC Electrical Characteristics
(SOIC Package)
Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
CC
C
L
=
50 pF,
R
L
=
500Ω
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
−1.2
2.5
2.0
0.7
−0.8
3.0
1.7
0.7
0.9
1.0
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
T
A
=
25°C (Note 6)
T
A
=
25°C (Note 6)
T
A
=
25°C (Note 7)
T
A
=
25°C (Note 8)
T
A
=
25°C (Note 8)
Note 6:
Max number of outputs defined as (n). n
−
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7:
Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 8:
Max number of data inputs (n) switching. n
−
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Packages)
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEAB to B
n
, LEBA to A
n
OEBA or OEAB to A
n
or B
n
t
PZH
t
PZL
Enable Time
LEAB to B
n
, LEBA to A
n
OEBA or OEAB to A
n
or B
n
t
PHZ
t
PLZ
Disable Time
CEBA or CEAB to A
n
or B
n
1.5
1.5
2.0
2.0
4.0
3.6
5.8
5.8
6.5
6.5
1.5
1.5
2.0
2.0
5.8
5.8
6.5
6.5
ns
ns
1.6
1.6
3.4
5.3
5.3
1.6
1.6
5.3
5.3
ns
1.5
1.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
3.1
Max
4.8
4.8
1.5
1.5
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
50 pF
Min
Max
4.8
4.8
ns
Units
AC Operating Requirements
(SOIC and SSOP Packages)
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
C
L
=
50 pF
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(L)
Setup Time, HIGH or LOW
A
n
or B
n
to LEBA or LEAB
Hold Time, HIGH or LOW
A
n
or B
n
to LEBA or LEAB
Setup Time, HIGH or LOW
A
n
or B
n
to CEAB or CEBA
Hold Time, HIGH or LOW
A
n
or B
n
to CEAB or CEBA
Pulse Width, LOW
1.5
1.5
1.0
1.0
1.5
1.5
1.3
1.3
3.0
Max
Min
1.5
1.5
1.0
1.0
1.5
1.5
1.3
1.3
3.0
ns
ns
ns
ns
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
50 pF
Max
ns
Units
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4
74ABT543
Extended AC Electrical Characteristics
(SOIC Package)
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
Symbol
Parameter
C
L
=
50 pF
8 Outputs Switching
(Note 9)
Min
f
TOGGLE
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
Max Toggle Frequency
Propagation Delay
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEAB to B
n
, LEBA to A
n
Output Enable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
t
PHZ
t
PLZ
Output Disable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
1.5
1.5
8.5
8.5
(Note 12)
(Note 12)
ns
1.5
1.5
7.5
7.5
2.0
2.0
8.5
8.5
2.5
2.5
11.0
11.0
ns
1.5
1.5
1.5
1.5
Typ
100
6.2
6.2
6.5
6.5
2.0
2.0
2.0
2.0
7.5
7.5
8.0
8.0
2.5
2.5
2.5
2.5
10.0
10.0
10.5
10.5
ns
Max
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
250 pF
1 Output Switching
(Note 10)
Min
Max
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
250 pF
8 Outputs Switching
(Note 11)
Min
Max
MHz
ns
Units
Note 9:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 10:
This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 11:
This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 12:
The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet
Skew
(SOIC Package)
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
Symbol
Parameter
C
L
=
50 pF
8 Outputs Switching
(Note 13)
Max
t
OSHL
(Note 15)
t
OSLH
(Note 15)
t
PS
(Note 16)
t
OST
(Note 15)
t
PV
(Note 17)
Pin to Pin Skew
HL Transitions
Pin to Pin Skew
LH Transitions
Duty Cycle
LH–HL Skew
Pin to Pin Skew
LH/HL Transitions
Device to Device Skew
LH/HL Transitions
2.5
4.5
ns
2.0
4.0
ns
2.0
4.0
ns
1.3
2.0
ns
1.0
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
250 pF
8 Outputs Switching
(Note 14)
Max
2.0
ns
Units
Note 13:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 14:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 15:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
). This specification is guaranteed but not tested.
Note 16:
This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 17:
Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
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