74ABT273 Octal D-Type Flip-Flop
January 1993
Revised November 1999
74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Buffered, asynchronous Master Reset
s
See ABT377 for clock enable version
s
See ABT373 for transparent latch version
s
See ABT374 for 3-STATE version
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Order Number
74ABT273CSC
74ABT273CSJ
74ABT273CMSA
74ABT273CMTC
Package Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
Description
© 1999 Fairchild Semiconductor Corporation
DS011549
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74ABT273
Truth Table
Operating Mode
MR
Reset (Clear)
Load “1”
Load “0”
L
H
H
Inputs
CP
D
n
X
h
l
Output
Q
n
L
H
L
H
=
HIGH Voltage Level steady state
h
=
HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L
=
LOW Voltage Level steady state
I
=
LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X
=
Immaterial
=
LOW-to-HIGH clock transition
X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ABT273
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup
V
CC
+
4.5V
twice the rated I
OL
(mA)
−500
mA
−0.5V
to
+4.75V
−0.5V
to V
CC
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (∆V/∆t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
−40°C
to
+85°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OS
I
CEX
I
CCH
I
CCL
I
CCT
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input LOW Current
Input Leakage Test
Output Short-Circuit Current
Output HIGH Leakage Current
Power Supply Current
Power Supply Current
Maximum I
CC
/Input
Outputs Enabled
4.75
−100
−275
50
50
30
1.5
2.5
2.0
0.55
1
1
7
−1
−1
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
mA
µA
µA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
Max
Max
Max
Max
Max
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18
mA
I
OH
= −3
mA
I
OH
= −32
mA
I
OL
=
64 mA
V
IN
=
2.7V (Note 3)
V
IN
=
V
CC
V
IN
=
7.0V
V
IN
=
0.5V (Note 3)
V
IN
=
0.0V
I
ID
=
1.9
µA
All Other Pins Grounded
V
OUT
=
0.0V
V
OUT
=
V
CC
All Outputs HIGH
All Outputs LOW
V
I
=
V
CC
−
2.1V
Data Input V
I
=
V
CC
−
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
0.3
mA/
MHz
Note 3:
Guaranteed but not tested.
Note 4:
For 8 bits toggling, I
CCD
<
0.5 mA/MHz.
Max
Outputs Open (Note 4)
One Bit Toggling, 50% Duty Cycle
3
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74ABT273
AC Electrical Characteristics
(SSOIC package)
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PHL
Maximum Clock Frequency
Propagation Delay
CP to O
n
Propagation Delay
MR to O
n
150
2.0
2.8
2.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
200
6.0
6.8
7.4
Max
T
A
= −55°C
to
+125°C
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
Min
150
1.0
1.0
1.0
7.0
7.5
8.2
Max
T
A
= −40°C
to
+85°C
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
Min
150
2.0
2.8
2.5
6.0
6.8
7.4
Max
MHz
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
C
L
=
50 pF
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH
or LOW D
n
to CP
Hold Time, HIGH
or LOW D
n
to CP
Pulse Width, CP,
HIGH or LOW
Master Reset Pulse
Width, LOW
Recovery Time
MR to CP
2.0
2.5
1.2
1.2
3.3
3.3
3.3
2.0
Max
T
A
= −55°C
to
+125°C
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
Min
2.0
2.5
1.4
1.4
3.3
3.3
3.3
2.0
Max
T
A
= −40°C
to
+85°C
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
Min
2.0
2.5
1.2
1.2
3.3
3.3
3.3
2.0
Max
ns
ns
ns
ns
ns
Units
Capacitance
(SOIC package)
Symbol
C
IN
C
OUT
(Note 5)
Parameter
Input Capacitance
Output Capacitance
Typ
5
9
Units
pF
pF
V
CC
=
0V
V
CC
=
5.0V
Conditions
T
A
=
25°C
Note 5:
C
OUT
is measured at frequency f
=
1 MHz, per MIL-STD-833, Method 3012.
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4
74ABT273
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. V
M
=
1.5V
Input Pulse Requirements
Amplitude
3.0V
Rep. Rate
1 MHz
t
W
500 ns
t
r
2.5 ns
t
f
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 6. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 4. Propagation Delay,
Pulse Width Waveforms
FIGURE 5. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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