74ABT2244 Octal Buffer/Line Driver with 25
Ω
Series Resistors in the Outputs
March 2007
74ABT2244
Octal Buffer/Line Driver with 25
Ω
Series Resistors
in the Outputs
Features
■
Guaranteed latchup protection
■
High-impedance, glitch-free bus loading during entire
tm
General Description
The ABT2244 is an octal buffer and line driver designed
to drive the capacitive inputs of MOS memory drivers,
address drivers, clock drivers, and bus-oriented trans-
mitters/receivers.
The 25
Ω
series resistors in the outputs reduce ringing
and eliminate the need for external resistors.
power up and power down cycle
■
Nondestructive, hot-insertion capability
Ordering Information
Order Number
74ABT2244CSC
74ABT2244CSJ
74ABT2244CMSA
74ABT2244CMTC
Package
Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Schematic of Each Output
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Inputs
Outputs
Description
Output Enable Input (Active LOW)
Truth Table
OE
1
H
L
L
I
0–3
X
H
L
O
0–3
Z
H
L
OE
2
H
L
L
I
4–7
X
H
L
O
4–7
Z
H
L
H
=
HIGH Voltage Level X
=
Immaterial
L
=
LOW Voltage Level
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
Z
=
High Impedance
www.fairchildsemi.com
74ABT2244 Octal Buffer/Line Driver with 25
Ω
Series Resistors in the Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
A
T
J
V
CC
V
IN
I
IN
V
O
Storage Temperature
Parameter
Ambient Temperature Under Bias
Junction Temperature Under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage
(1)
Input Current
(1)
Voltage Applied to Any Output
Disabled or Power-off State
HIGH State
Current Applied to Output in LOW State (Max.)
DC Latchup Source Current (Across Comm Operating Range)
Over Voltage Latchup (I/O)
Rating
–65°C to +150°C
–55°C to +125°C
–55°C to +150°C
–0.5V to +7.0V
–0.5V to +7.0V
–30mA to +5.0mA
–0.5V to 5.5V
–0.5V to V
CC
twice the rated I
OL
(mA)
–300mA
10V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
T
A
V
CC
∆
V /
∆
t
Supply Voltage
Minimum Input Edge Rate
Data Input
Enable Input
Parameter
Free Air Ambient Temperature
Rating
–40°C to +85°C
+4.5V to +5.5V
50mV/ns
20mV/ns
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
2
74ABT2244 Octal Buffer/Line Driver with 25
Ω
Series Resistors in the Outputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Power Supply Current
Additional
I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
I
CCD
Dynamic I
CC
No Load
(3)
Max.
Max.
Max.
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Max.
Max.
0.0
Max.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown
Test
Input LOW Current
Input Leakage Test
Output Leakage Current
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min.
2.0
Typ.
Max. Units
V
0.8
–1.2
V
V
V
0.8
1
1
7
–1
–1
µA
µA
V
10
–10
µA
mA
µA
µA
µA
mA
µA
mA
mA
µA
mA/
MHz
V
µA
Min.
Min.
Min.
Max.
Max.
Max.
0.0
I
IN
=
–18mA
I
OH
=
–3mA
I
OH
=
–32mA
I
OL
=
15mA
V
IN
=
2.7V
(3)
V
IN
=
V
CC
V
IN
=
7.0V
V
IN
=
0.5V
(3)
V
IN
=
0.0V
I
ID
=
1.9µA, All Other Pins
Grounded
V
OUT
=
0.5V; OEn
=
2.0V
V
OUT
=
0.0V
V
OUT
=
V
CC
V
OUT
=
5.5V, All Others GND
All Outputs HIGH
All Outputs LOW
OEn
=
V
CC
, All Others at V
CC
or GND
V
I
=
V
CC
– 2.1V
Enable Input V
I
=
V
CC
– 2.1V
Data Input V
I
=
V
CC
– 2.1V,
All Others at V
CC
or GND
–100
475
2.5
2.0
0–5.5V V
OUT
=
2.7V; OEn
=
2.0V
–275
50
100
50
30
50
2.5
2.5
50
0.1
Outputs OPEN, OEn
=
GND
(2)
,
One-Bit Toggling,
50% Duty Cycle
Notes:
1. Either voltage limit or current limit is sufficient to protect inputs.
2. For 8-bit toggling, I
CCD
<
0.8mA/MHz.
3. Guaranteed, but not tested.
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
3
74ABT2244 Octal Buffer/Line Driver with 25Ω Series Resistors in the Outputs
AC Electrical Characteristics
SOIC and SSOP packages.
T
A
=
+25°C,
V
CC
=
+5V,
C
L
=
50pF
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
T
A
=
–40°C to +85°C,
V
CC
=
4.5V–5.5V,
C
L
=
50pF
Max.
3.9
4.4
6.0
7.0
5.8
5.8
Parameter
Propagation Delay,
Data to Outputs
Output Enable Time
Min.
1.0
1.0
1.5
2.1
1.7
1.7
Typ.
2.2
2.9
3.7
4.3
3.5
3.7
Min.
1.0
1.0
1.5
2.1
1.7
1.7
Max.
3.9
4.4
6.0
7.0
5.8
5.8
Units
ns
ns
ns
Capacitance
Symbol
C
IN
C
OUT(4)
Parameter
Input Capacitance
Output Capacitance
Conditions
(T
A
=
25°C)
V
CC
=
0V
V
CC
=
5.0V
Typ.
5.0
9.0
Units
pF
pF
Note:
4. C
OUT
is measured at frequency f
=
1MHz, per MIL-STD-883, Method 3012.
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
4
74ABT2244 Octal Buffer/Line Driver with 25Ω Series Resistors in the Outputs
AC Loading
*Includes jig and probe capacitance
Figure 1. Standard AC Test Load
Figure 2. Test Input Signal Levels
Amplitude
3.0V
Rep. Rate
1MHz
t
w
500ns
t
r
2.5ns
t
f
2.5ns
Figure 3. Test Input Signal Requirements
AC Waveforms
Figure 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
Figure 5. 3-STATE Output HIGH and LOW Enable
and Disable Times
Figure 6. Propagation Delay, Pulse Width Waveforms
Figure 7. Setup Time, Hold Time
and Recovery Time Waveforms
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
5
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