74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs
October 1993
Revised January 1999
74ABT16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ABT16543 16-bit transceiver contains two sets of D-
type latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. Each byte has separate control inputs, which can be
shorted together for full 16-bit operation.
Features
s
Back-to-back registers for storage
s
Bidirectional data path
s
A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA
s
Separate control logic for each byte
s
16-bit version of the ABT543
s
Separate controls for data flow in each direction
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT16543CSSC
74ABT16543CMTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names
OEAB
n
OEBA
n
CEAB
n
CEBA
n
LEAB
n
LEBA
n
A
0
–A
15
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
–B
15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation
DS011646.prf
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74ABT16543
Logic Symbol
Data I/O Control Table
Inputs
CEAB
n
LEAB
n
OEAB
n
H
X
L
X
L
X
H
L
X
X
X
X
X
H
L
Latch Status Output Buffers
(Byte n)
Latched
Latched
Transparent
—
—
(Byte n)
HIGH Z
—
—
HIGH Z
Driving
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
A-to-B data flow shown;
B-to-A flow control is the same, except using CEBA
n
, LEBA
n
and OEBA
n
Functional Description
The ABT16543 contains two sets of D-type latches, with
separate input and output controls for each. For data flow
from A to B, for example, the A to B Enable (CEAB) input
must be low in order to enter data from the A port or take
data from the B-Port as indicated in the Data I/O Control
Table. With CEAB low, a low signal on (LEAB) input makes
the A to B latches transparent; a subsequent low to high
transition of the LEAB line puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both low, the B output buffers are
active and reflect the data present on the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA. Each byte has separate con-
trol inputs, allowing the device to be used as two 8-bit
transceivers or as one 16-bit transceiver.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
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2
74ABT16543
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disable or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to
+5.5V
−0.5V
to V
CC
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500
mA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (∆V/∆t)
Data Input
Enable Input
Clock Input
50 mV/ns
20 mV/ns
100 mV/ns
−40°C
to
+85°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
V
ID
I
IH
I
BVI
I
BVIT
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Test
Input HIGH Current
Input HIGH Current Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
−1
−1
I
IH
+
I
OZH
Output Leakage Current
I
IL
+
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
I
CCD
Output Leakage Current
−100
10
−10
−275
50
100
1.0
60
1.0
2.5
No Load
0.25
mA/MHz
Max
µA
µA
mA
µA
µA
mA
mA
mA
mA
µA
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 3)
V
IN
=
0.0V (Non-I/O Pins)
0V–5.5V V
OUT
=
2.7V (A
n
, B
n
);
OEAB or CEAB
=
2V
0V–5.5V V
OUT
=
0.5V (A
n
, B
n
);
OEAB or CEAB
=
2V
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Dynamic I
CC
(Note 3)
Max
Max
0.0V
Max
Max
Max
Max
V
OUT
=
0V (A
n
, B
n
)
V
OUT
=
V
CC
(A
n
, B
n
)
V
OUT
=
5.5V (A
n
, B
n
); All Others GND
All Outputs HIGH
All Outputs LOW
Outputs 3-STATE
All Others at V
CC
or GND
V
I
=
V
CC
−
2.1V
All Others at V
CC
or GND
Outputs Open, CEAB, OEAB, LEAB
=
GND,
CEBA
=
V
CC
, One Bit Toggling,
50% Duty Cycle
Note 3:
Guaranteed but not tested.
Min
2.0
Typ
Max
Units
V
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
0.8
−1.2
2.5
2.0
0.55
4.75
1
1
7
100
V
V
Min
I
IN
= −18
mA (Non I/O Pins)
I
OH
= −3
mA, (A
n
, B
n
)
I
OH
= −32
mA, (A
n
, B
n
)
V
V
µA
µA
µA
Min
0.0
Max
Max
Max
I
OL
=
64 mA, (A
n
, B
n
)
I
ID
=
1.9
µA,
(Non-I/O Pins)
All Other Pins Grounded
V
IN
=
2.7V (Non-I/O Pins) ((Note 3)
V
IN
=
V
CC
(Non-I/O Pins)
V
IN
=
7.0V (Non-I/O Pins)
V
IN
=
5.5V (A
n
, B
n
)
3
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74ABT16543
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEAB
n
to B
n
, LEBA
n
to A
n
Enable Time
OEBA
n
or OEAB
n
to A
n
or B
n
Disable Time
OEAB
n
or OEBA
n
to A
n
or B
n
Enable Time
CEBA
n
or CEAB
n
to A
n
or B
n
Disable Time
CEBA
n
or CEAB
n
to A
n
or B
n
1.7
3.2
6.3
1.7
6.3
ns
1.5
3.1
6.2
1.5
6.2
ns
1.6
3.1
6.0
1.6
6.0
ns
1.5
2.8
5.2
1.5
5.2
ns
1.5
3.0
5.5
1.5
5.5
ns
1.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
3.0
Max
5.7
1.5
T
A
= −55°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
50 pF
Min
Max
5.7
ns
Units
AC Operating Requirements
(SSOP Package)
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
C
L
=
50 pF
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(L)
Setup Time, HIGH or LOW
A
n
or B
n
to LEBA
n
or LEAB
n
Hold Time, HIGH or LOW
A
n
or B
n
to LEBA
n
or LEAB
n
Pulse Width, LOW
2.0
2.0
1.0
1.0
3.0
Max
Min
2.0
2.0
1.0
1.0
3.0
ns
ns
T
A
= −55°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
50 pF
Max
ns
Units
Capacitance
Symbol
C
IN
C
I/O
(Note 4)
Parameter
Input Capacitance
Output Capacitance
Typ
5.0
11.0
Units
pF
pF
Conditions
T
A
=
25°C
V
CC
=
0V (non I/O pins)
V
CC
=
5.0V (A
n
, B
n
)
Note 4:
C
I/O
is measured at frequency, f
=
1 MHz, per MIL-STD-883, Method 3012.
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4
74ABT16543
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
Input Pulse Requirements
Amplitude
3V
Rep. Rate
1 MHz
t
W
500 ns
t
r
2.5 ns
FIGURE 2. V
M
=
1.5V
t
f
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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