www.fairchildsemi.com
FAN5009
Dual Bootstrapped 12V MOSFET Driver
Features
• Drives N-channel High-Side and Low-Side MOSFETs in
a synchronous buck configuration
• 12V High-Side and 12V Low-Side Drive
• Internal Adaptive “Shoot-Through” Protection
• Integrated Bootstrap Diode for High-Side Drive
• Fast rise and fall times
• Switching Frequency Up to 500kHz
• OD input for Output Disable – allows for synchronization
with PWM controller
• SOIC-8 Package
• Available in low thermal resistance MLP package
General Description
The FAN5009 is a dual, high frequency MOSFET driver,
specifically designed to drive N-Channel power MOSFETs
in a synchronous-rectified buck converter. These drivers,
combined with a Fairchild Multi-Phase PWM controller and
power MOSFETs, form a complete core voltage regulator
solution for advanced microprocessors.
The FAN5009 drives the upper and lower MOSFET gates of
a synchronous buck regulator to 12V
GS
. The upper gate
drive includes an integrated boot diode and requires only an
external bootstrap capacitor (C
BOOT
). The output drivers in
the FAN5009 have the capacity to efficiently switch power
MOSFETs at frequencies up to 500kHz. The circuit’s
adaptive shoot-through protection prevents the MOSFETs
from conducting simultaneously.
The FAN5009 is rated for operation from 0°C to +85°C and
is available in low-cost SOIC-8 or MLP packages.
Applications
• Multi-phase VRM/VRD regulators for Microprocessor
Power
• High Current/High Frequency DC/DC Converters
• High Power Modular Supplies
Typical Application
12V
FAN5009
4
VCC
C
VCC
1
BOOT
Q1
C
BOOT
PWM
2
8
HDRV
SW
Q2
L1
V
OUT
C
OUT
OD
3
OVERLAP
PROTECTION
CIRCUIT
7
VCC
5
LDRV
PGND
6
Figure 1. Typical Application.
REV. 1.0.5 7/22/04
FAN5009
PRODUCT SPECIFICATION
Pin Configuration
Paddle
(Ground)
BOOT
PWM
OD
VCC
1
2
3
4
FAN5009
8
7
6
5
HDRV
SW
PGND
LDRV
BOOT 1
PWM
2
OD 3
VCC 4
FAN5009
8
7
6
5
HDRV
SW
PGND
LDRV
FAN5009M 8-pin SO-8 package
FAN5009MP 8-pin MLP package
(Paddle should be connected to ground or left floating)
Pin Definitions
Pin # Pin Name
1
2
3
4
5
6
7
8
BOOT
PWM
OD
VCC
LDRV
PGND
SW
HDRV
Pin Function Description
Bootstrap Supply Input.
Provides voltage supply to high-side MOSFET driver. Connect to
bootstrap capacitor. See Applications Section.
PWM Signal Input.
This pin accepts a logic-level PWM signal from the controller.
Output Disable.
When low, this pin disables FET switching (HDRV and LDRV are held low).
Power Input
. +12V chip bias power. Bypass with a 1µF ceramic capacitor.
Low Side Gate Drive Output.
Connect to the gate of low-side power MOSFET(s).
Power ground.
Connect directly to source of low-side MOSFET(s).
Switch Node Input
. Connect as shown in Figure 1. SW provides return for high-side
bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection.
High Side Gate Drive Output
–
Connect to the gate of high-side power MOSFET(s).
Functional Block Diagram
4
VCC
BOOT
HDRV
OD
PWM
2
3
1
8
+
2.2
1.2
7
SW
1.2
VCC
5
6
LDRV
PGND
2
REV. 1.0.5 7/22/04
PRODUCT SPECIFICATION
FAN5009
Absolute Maximum Ratings
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or other conditions beyond those indicated in
the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability. Absolute maximum ratings apply individually, not in combination.
Unless otherwise specified, voltages are referenced to PGND.
Parameter
VCC to PGND
PWM and OD pins
SW to PGND
BOOT to SW
BOOT to PGND
HDRV
LDRV
Continuous
Transient ( t=200nsec)
Notes:
1. For transient derating beyond the levels indicated, refer to the graphs on page 7.
Min.
–0.3
–0.3
Continuous
Transient ( t=100nsec, F
≤
500kHz)
Continuous
Transient ( t=100nsec, F
≤
500kHz)
V
SW
–1
–0.5
–2
(1)
–1
–5
(1)
–0.3
–0.3
Max.
15
5.5
15
25
15
30
33
(1)
V
BOOT
+0.3
V
CC
+0.3
Units
V
V
V
V
V
V
V
V
V
V
Thermal Information
Parameter
Junction Temperature (T
J
)
Storage Temperature
Lead Soldering Temperature, 10 seconds
Vapor Phase, 60 seconds
Infrared, 15 seconds
Power Dissipation (P
D
) T
A
= 25°C
Thermal Resistance, SO8 – Junction to Case
θ
JC
Thermal Resistance, SO8 – Junction to Ambient
θ
JA
Thermal Resistance, MLP – Junction to Paddle
θ
JC
40
140
4
Min.
0
–65
Typ.
Max.
150
150
300
215
220
715
Units
°C
°C
°C
°C
°C
mW
°C/W
°C/W
°C/W
Recommended Operating Conditions
Parameter
Supply Voltage VCC
Ambient Temperature (T
A
)
Junction Temperature (T
J
)
Conditions
VCC to PGND
Min.
10
0
0
Typ.
12
Max.
13.5
85
125
Units
V
°C
°C
REV. 1.0.5 7/22/04
3
FAN5009
PRODUCT SPECIFICATION
Electrical Specifications
V
CC
= 12V, and T
A
= 25°C using circuit in Figure 2 unless otherwise noted. The • denotes specifications which apply
over the full operating temperature range.
Parameter
Input Supply
VCC Voltage Range
VCC Current
Bootstrap Diode
Continuous Forward Current
Reverse Breakdown Voltage
Reverse Recovery Time
2
Forward Voltage
2
OD Input
Input High Voltage
Input Low Voltage
Input Current
Propagation Delay
2
PWM Input
Input High Voltage
Input Low Voltage
Input Current
High-Side Driver
Output Resistance, Sourcing
Current
Output Resistance, Sinking
Current
Transition Times
2,4
Propagation Delay
2,3
R
HUP
R
HDN
t
R(HDRV)
t
F(HDRV)
t
pdh(HDRV)
t
pdl(HDRV)
See Figure 2, and 4
V
BOOT
–V
SW
= 12V
V
BOOT
–V
SW
= 12V
See Figure 2
3.8
1.4
40
20
50
25
4.4
1.8
55
30
65
40
Ω
Ω
ns
ns
ns
ns
V
IH(PWM)
V
IL(PWM)
I
IL(PWM)
•
•
•
-1
3.5
0.8
+1
V
V
µ
A
V
IH (OD)
V
IL (OD)
I
OD
t
pdl(OD)
t
pdh(OD)
OD = 3.0V
See Figure 3
•
•
•
–300
30
30
2.5
0.8
+300
40
45
V
V
nA
ns
ns
I
F(AVG)
V
R
t
RR
V
F
I
F
= 10mA
•
•
15
10
0.8
0.95
25
mA
V
ns
V
V
CC
I
CC
OD = 0V
•
•
6.4
12
3.5
13.5
8
V
mA
Symbol
Conditions
Min.
Typ.
Max.
Units
12V
33K
FAN5009
1 BOOT
2 PWM
3 OD
HDRV 8
SW 7
PGND 6
LDRV 5
3000pf
3000pf
10K
4 VCC
1µf
Figure 2. Test Circuit
4
REV. 1.0.5 7/22/04
PRODUCT SPECIFICATION
FAN5009
Electrical Specifications
(continued)
Parameter
Low-Side Driver
Output Resistance, Sourcing
Current
Output Resistance, Sinking
Current
Transition Times
2,4
Propagation Delay
2,3
R
LUP
R
LDN
t
R(LDRV)
t
F(LDRV)
t
pdh(LDRV)
t
pdl(LDRV)
t
pdh(ODRV)
See Adaptive Gate
Drive Circuit
description
See Figures 2, 4
See Figure 2
3.4
1.4
40
20
20
25
240
4.0
1.8
50
30
30
40
Ω
Ω
ns
ns
ns
ns
ns
Symbol
Conditions
Min.
Typ.
Max.
Units
NOTES:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. AC Specifications guaranteed by design/characterization (not production tested).
3. For propagation delays, “tpdh” refers to low-to-high signal transition and “tpdl” refers to high-to-low signal transition
4. Transition times are defined for 10% and 90% of DC values
V
IH(OD)
OD
V
IL(OD)
t
pdl(OD)
t
pdh(OD)
LDRV / HDRV
Figure 3. Output Disable Timing
V
IH(PWM)
PWM
t
pdl (LDRV)
V
IL(PWM)
LDRV
1.2V
t
pdh(HDRV)
t
pdl (HDRV)
HDRV-SW
t
pdh(LDRV)
SW
2.2V
Figure 4. Adaptive Gate Drive Timing
REV. 1.0.5 7/22/04
5
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