74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker
November 1992
Revised January 1999
74ABT899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
The ABT899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction.
The ABT899 features independent latch enables for the A-
to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
s
Ability to simultaneously generate and check parity
s
May be used in systems applications in place of the
543 and 280
s
May be used in system applications in place of the
657 and 373 (no need to change T/R to check parity)
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and
250 pF loads
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
s
Disable time less than enable time to avoid bus
contention
Features
s
Latchable transceiver with output sink of 64 mA
s
Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
s
Independent latch enables for A-to-B and B-to-A
directions
s
Select pin for ODD/EVEN parity
s
ERRA and ERRB output pins for parity checking
Ordering Code:
Order Number
74ABT899CSC
74ABT899CMSA
74ABT899CQC
Package Number
M28B
MSA28
V28A
Package Description
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment
for PLCC
Pin Assignment for
SOIC and SSOP
© 1999 Fairchild Semiconductor Corporation
DS011509.prf
www.fairchildsemi.com
74ABT899
Pin Descriptions
Pin Names
A
0
–A
7
B
0
–B
7
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
Descriptions
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs/Outputs
ODD/EVEN Parity Select,
Active LOW for EVEN Parity
Output Enables for A or B Bus,
Active LOW
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Latch Enables for A and B Latches,
HIGH for Transparent Mode
Error Signals for Checking Generated
Parity with Parity In, LOW if Error
Occurs
Functional Description
The ABT899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
• Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
• Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
• Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table below).
LEA, LEB
ERRA, ERRB
Function Table
Inputs
GAB GBA SEL LEA LEB
H
H
H
H
L
L
X
L
L
X
L
H
X
H
H
Busses A and B are 3-STATE.
Generates parity from B[0:7] based on O/E (Note 1). Generated parity
→
APAR.
Generated parity checked against BPAR and output as ERRB.
Generates parity from B[0:7] based on O/E. Generated parity
→
APAR. Gener-
ated parity checked against BPAR and output as ERRB. Generated parity also
fed back through the A latch for generate/check as ERRA.
Generates parity from B latch data based on O/E. Generated parity
→
APAR.
Generated parity checked against latched BPAR and output as ERRB.
BPAR/B[0:7]
→
APAR/A0:7] Feed-through mode. Generated parity checked
against BPAR and output as ERRB.
BPAR/B[0:7]
→
APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and output as
ERRB. Generated parity also fed back through the A latch for generate/check as
ERRA.
L
L
H
H
L
L
H
H
L
H
Generates parity for A[0:7] based on O/E. Generated parity
→
BPAR. Gener-
ated parity checked against APAR and output as ERRA.
Generates parity from A[0:7] based on O/E. Generated parity
→
BPAR. Gener-
ated parity checked against APAR and output as ERRA. Generated parity also
fed back through the B latch for generate/check as ERRB.
Generates parity from A latch data based on O/E. Generated parity
→
BPAR.
Generated parity checked against latched APAR and output as ERRA.
APAR/A[0:7]
→
BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as
ERRA.
L
H
H
H
H
APAR/A[0:7]
→
BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as
ERRA. Generated parity also fed back through the B latch for generate/check as
ERRB.
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Note 1:
O/E
=
ODD/EVEN
Operation
H
H
H
L
L
L
L
H
H
X
X
H
L
H
H
L
L
H
H
L
H
L
H
X
L
www.fairchildsemi.com
2
74ABT899
Functional Block Diagram
3
www.fairchildsemi.com
74ABT899
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Any Output
in the Disable or Power-
Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to
+5.5V
−0.5V
to V
CC
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
−55°C
to
+150°C
−65°C
to
+150°C
−55°C
to
+125°C
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500
mA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (∆V/∆t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
−40°C
to
+85°C
+4.5V
to
+5.5V
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
V
ID
I
IH
I
BVI
I
BVIT
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW Voltage
Input Leakage Test
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
−5
50
−50
−100
−275
50
100
250
34
250
2.5
0.4
µA
µA
µA
mA
µA
µA
µA
mA
µA
mA
mA/MHz
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 4)
V
IN
=
0.0V (Non-I/O Pins)
I
IH
+
I
OZH
Output Leakage Current
I
IL
+
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
I
CCD
Output Leakage Current
0V–5.5V V
OUT
=
2.7V (A
n
, B
n
);
GAB and GBA
=
2.0V
0V–5.5V V
OUT
=
0.5V (A
n
, B
n
);
GAB and GBA
=
2.0V
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Dynamic I
CC
:
(Note 4)
No Load
Max
Max
0.0V
Max
Max
Max
Max
Max
V
OUT
=
0V (A
n
, B
n
, APAR, BPAR)
V
OUT
=
V
CC
(A
n
, B
n
, APAR, BPAR)
V
OUT
=
5.5V (A
n
, B
n
, APAR, BPAR);
All Others GND
All Outputs HIGH
All Outputs LOW, ERRA/B
=
HIGH (Note 5)
Outputs 3-STATE All Others at V
CC
or GND
V
I
=
V
CC
−
2.1V All Others at V
CC
or GND
Outputs Open
GAB or GBA
=
GND, LE
=
HIGH
Non-I/O
=
GND or V
CC
One bit toggling, 50% duty cycle
Note 4:
Guaranteed, but not tested.
Note 5:
Add 3.75 mA for each ERR LOW.
Min
2.0
Typ
Max
Units
V
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
0.8
−1.2
2.5
2.0
0.55
4.75
5
7
100
V
V
V
V
V
µA
µA
µA
Min
Min
Min
0.0
Max
Max
Max
I
IN
= −18
mA (Non I/O Pins)
I
OH
= −3
mA, (A
n
, B
n
, APAR, BPAR)
I
OH
= −32
mA, (A
n
, B
n
, APAR, BPAR)
I
OL
=
64 mA, (A
n
, B
n
, APAR, BPAR)
I
ID
=
1.9
µA,
(Non-I/O Pins)
All Other Pins Grounded
V
IN
=
2.7V (Non-I/O Pins) (Note 4)
V
IN
=
V
CC
(Non-I/O Pins)
V
IN
=
7.0V (Non-I/O Pins)
V
IN
=
5.5V (A
n
, B
n
, APAR, BPAR)
www.fairchildsemi.com
4
74ABT899
DC Electrical Characteristics
(PLCC package)
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
−1.3
2.5
2.2
Min
Typ
0.8
−0.8
3.0
1.8
0.8
0.5
Max
1.1
Units
V
V
V
V
V
V
CC
5.0
5.0
5.0
5.0
5.0
Conditions
C
L
=
50 pF, R
L
=
500Ω
T
A
=
25°C (Note 6)
T
A
=
25°C (Note 6)
T
A
=
25°C (Note 8)
T
A
=
25°C (Note 7)
T
A
=
25°C (Note 7)
Note 6:
Max number of outputs defined as (n). n
−
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7:
Max number of data inputs (n) switching. n
−
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
Note 8:
Max number of outputs defined as (n). n
−
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and PLCC Package)
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
Propagation Delay
A
n
, to B
n
Propagation Delay
A
n
, B
n
to BPAR, APAR
Propagation Delay
A
n
, B
n
to ERRA, ERRB
Propagation Delay
APAR, BPAR to ERRA, ERRB
Propagation Delay
ODD/EVEN to APAR, BPAR
Propagation Delay
ODD/EVEN to ERRA, ERRB
Propagation Delay
SEL to APAR, BPAR
Propagation Delay
LEA, LEB to B
n
, A
n
Propagation Delay
LEA, LEB to BPAR, APAR
Generate Mode
Propagation Delay
LEA, LEB to BPAR, APAR,
Feed Thru Mode
Propagation Delay
LEA, LEB to ERRA, ERRB
Output Enable Time
GBA or GAB to A
n
,
APAR or B
n
, BPAR
Output Disable Time
GBA or GAB to A
n
,
APAR or B
n
, BPAR
Propagation Delay
APAR to BPAR, BPAR to APAR
1.5
1.5
3.3
3.8
5.4
5.4
1.5
1.5
5.4
5.4
ns
1.0
1.0
4.0
3.3
6.0
6.0
1.0
1.0
6.0
6.0
ns
1.6
1.6
1.5
1.5
5.4
5.4
3.6
3.4
8.4
8.4
6.0
6.0
1.6
1.6
1.5
1.5
8.4
8.4
6.0
6.0
ns
ns
1.5
1.5
3.6
3.6
5.1
5.1
1.5
1.5
5.1
5.1
ns
1.5
1.5
2.5
2.5
2.5
2.5
1.5
1.5
2.0
2.0
1.8
1.8
1.5
1.5
1.5
1.5
2.5
2.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
3.0
3.5
5.9
5.8
5.4
5.4
3.7
3.7
4.4
4.4
4.0
4.0
3.8
3.8
3.2
3.2
5.9
5.7
Max
4.8
4.8
9.2
9.2
8.5
8.5
6.0
6.0
6.9
6.9
6.0
6.0
6.0
6.0
4.6
4.6
8.8
8.8
1.5
1.5
2.5
2.5
2.5
2.5
1.5
1.5
2.0
2.0
1.8
1.8
1.5
1.5
1.5
1.5
2.5
2.5
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
50 pF
Min
Max
4.8
4.8
9.2
9.2
8.5
8.5
6.0
6.0
6.9
6.9
6.0
6.0
6.0
6.0
4.6
4.6
8.8
8.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
5
www.fairchildsemi.com
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
