Si597
Q
UAD
F
R E Q U E N C Y
V
O L TAG E
- C
O N T R O L L E D
C
RYSTAL
O
SCILLATOR
( V C X O ) 1 0
TO
810 MH
Z
Features
Available with any-frequency
output from 10 to 810 MHz
4 selectable output frequencies
3rd generation DSPLL
®
with
superior jitter performance
Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
Si5602
Applications
Ordering Information:
See page 8.
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
OTN
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
Description
The Si597 quad frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low-jitter clock for all output frequencies. The
Si597 is available with one of four pin-selectable ouput frequencies from 10
to 810 MHz. Unlike traditional VCXOs, where a different crystal is required
for each output frequency, the Si597 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides supply noise rejection, simplifying
the task of generating low-jitter clocks in noisy environments. The Si597 IC-
based quad frequency VCXO is factory-configurable for a wide variety of
user specifications including frequencies, supply voltage, output format,
tuning slope, and absolute pull range (APR). Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Pin Assignments:
See page 7.
(Top View)
FS[1]
7
V
C
1
6
V
DD
OE
2
5
CLK–
GND
3
8
FS[0]
4
CLK+
Functional Block Diagram
V
DD
P oo w e r S u p p ly F ilte rin g
P w e r S u p p ly F ilte rin g
OE
CLK+
F ixe d
F re q u e n cy
O s cilla to r
A n y F re q u e n c y
10–810 M H z
DSPLL
C lo c k S y n th e s is
CLK-
V
c
ADC
C o n tro l
GND
FS0
FS1
Rev. 1.1 6/18
Copyright © 2018 by Silicon Laboratories
Si597
Si597
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6. Si597 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Rev. 1.1
Si597
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
Tristate mode
Output Enable (OE)
2
and
Frequency Select (FS[1:0])
Operating Temperature Range
T
A
V
IH
V
IL
Min
2.97
2.25
1.71
—
—
—
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
120
110
100
90
60
—
—
—
Max
3.63
2.75
1.89
135
120
110
100
75
—
0.5
85
Unit
V
V
V
mA
mA
mA
mA
mA
V
V
°C
Notes:
1.
Selectable parameter specified by part number. See 3. "Ordering Information" on page 8 for further details.
2.
OE pin includes an internal 17 k pullup resistor to V
DD
for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 8. FS[1:0] includes internal 17 kpull-up to
VDD.
Table 2. V
C
Control Voltage Input
Parameter
Control Voltage Tuning Slope
1,2,3
Symbol
K
V
Test Condition
10 to 90% of V
DD
Min
—
—
—
—
—
–5
–10
9.3
500
—
@ f
O
—
0
Typ
45
95
125
185
380
±1
±5
10.0
—
50
V
DD
/2
—
Max
—
—
—
—
—
+5
+10
10.7
—
—
—
V
DD
Unit
ppm/V
Control Voltage Linearity
4
Modulation Bandwidth
V
C
Input Impedance
V
C
Input Capacitance
Nominal Control Voltage
Control Voltage Tuning Range
L
VC
BW
Z
VC
C
VC
V
CNOM
V
C
BSL
Incremental
%
%
kHz
k
pF
V
V
Notes:
1.
Positive slope; selectable option by part number. See 3. "Ordering Information" on page 8.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
K
V
variation is ±10% of typical values.
4.
BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.
Rev. 1.1
3
Si597
Table 3. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2,3
Temperature Stability
1,4
Absolute Pull Range
1,4
Power up Time
5
APR
t
OSC
Symbol
f
O
Test Condition
LVDS/CML/LVPECL
CMOS
T
A
= –40 to +85 ºC
V
DD
= 3.3 V
Min
10
10
–20
–50
±15
—
Typ
—
—
—
—
—
—
Max
810
160
+20
+50
±370
10
Unit
MHz
MHz
ppm
ppm
ppm
ms
Notes:
1.
See Section 3. "Ordering Information" on page 8 for further details.
2.
Specified at time of order by part number.
3.
Nominal output frequency set by V
CNOM
= V
DD
/2.
4.
Selectable parameter specified by part number. See “Ordering Information”.
5.
Time from power up or tristate mode to f
O
.
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.55
1.125
0.5
Typ
—
Max
V
DD
– 1.25
1.9
0.95
1.275
0.9
Unit
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.7
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
V
O
V
OD
2.5/3.3 V option mid-level
1.8 V option mid-level
2.5/3.3 V option swing
(diff)
1.8 V option swing
(diff)
—
—
1.10
0.35
0.8 x V
DD
V
DD
– 1.30
V
DD
– 0.36
1.50
0.425
—
—
—
2
—
—
—
1.90
0.50
V
DD
V
V
PP
V
V
PP
V
V
CMOS Output Option
3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
V
OH
V
OL
t
R,
t
F
—
LVPECL/LVDS/CML
CMOS with C
L
= 15 pF
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
—
—
45
0.4
350
—
55
ps
ns
%
SYM
Notes:
1.
50
to V
DD
– 2.0 V.
2.
R
term
= 100
(differential).
3.
C
L
= 15 pF. Sinking or sourcing 12 mA for V
DD
= 3.3 V, 6 mA for V
DD
= 2.5 V, 3 mA for V
DD
= 1.8 V.
4
Rev. 1.1
Si597
Table 5. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)
1,2
for F
OUT
of 50 MHz < F
OUT
<
810 MHz
Symbol
Test Condition
Kv = 45 ppm/V
12 kHz to 20 MHz
Kv = 95 ppm/V
12 kHz to 20 MHz
Kv = 125 ppm/V
12 kHz to 20 MHz
Kv = 185 ppm/V
12 kHz to 20 MHz
Kv = 380 ppm/V
12 kHz to 20 MHz
Min
—
—
—
—
—
Typ
0.5
0.5
0.5
0.5
0.7
Max
—
—
—
—
—
Unit
ps
ps
ps
ps
ps
J
Notes:
1.
Differential Modes: LVPECL/LVDS/CML. Refer to AN256 and AN266 for further information.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
Table 6. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
3
35
Max
—
—
Unit
ps
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency
74.25 MHz
185 ppm/V
LVPECL
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
–77
–101
–121
–134
–149
–151
–150
148.5 MHz
185 ppm/V
LVPECL
–68
–95
–116
–128
–144
–147
–148
155.52 MHz
95 ppm/V
LVPECL
–77
–101
–119
–127
–144
–147
–148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unit
Rev. 1.1
5
FPGA/CPLD
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