STC
FEATURES
Very Low Power/Voltage CMOS SRAM
256K X 16 bit
STC62WV25616
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
• Wide Vcc operation voltage : 2.4~5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 26mA (@55ns) operating current
I-grade: 27mA (@55ns) operating current
C-grade: 21mA (@70ns) operating current
I-grade: 22mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 63mA (@55ns) operating current
I-grade: 65mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I-grade: 55mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
DESCRIPTION
The
STC62WV25616
is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at 3.0V/25
o
C and maximum access time of 55ns at 3.0V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The
STC62WV25616
has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The
STC62WV25616
is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
PRODUCT FAMILY
PRODUCT FAMILY
STC62WV25616DC
STC62WV25616EC
STC62WV25616AC
STC62WV25616DI
STC62WV25616EI
STC62WV25616AI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(
ns )
55ns :3.0~5.5V
70ns :2.7~5.5V
( I
CCSB1
, Max )
POWER DISSIPATION
Operating
STANDBY
( I
CC
, Max )
PKG
TYPE
DICE
Vcc= 3.0V
Vcc= 5.0V
Vcc =3.0V
70ns
Vcc = 5.0V
70ns
+0 C to +70 C
O
O
2.4V ~ 5.5V
55 /70
5uA
30uA
21mA
53mA
-40 C to +85 C
O
O
2.4V ~ 5.5V
55 /70
10uA
60uA
22mA
55mA
TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 2048
62WV25616EC
62WV25616EI
2048
DQ0
16
Data
Input
Buffer
16
Column I/O
.
.
.
.
DQ15
.
.
.
.
Write Driver
Sense Amp
128
Column Decoder
16
Data
Output
16
Buffer
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5
STC International Limited
.
reserves the right to modify document contents without notice.
R0201-STC62WV25616
1
Revision 2.1
Jan.
2004
STC
PIN DESCRIPTIONS
STC62WV25616
Name
A0-A17 Address Input
CE Chip Enable Input
Function
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
Vcc
Gnd
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
CE
H
X
L
L
L
WE
X
X
X
H
H
OE
X
X
X
H
L
LB
X
H
H
X
L
Read
H
L
L
Write
L
L
X
H
L
UB
X
H
H
X
L
L
H
L
L
H
D0~D7
High Z
High Z
High Z
High Z
Dout
High Z
Dout
Din
X
Din
D8~D15
High Z
High Z
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
R0201-STC62WV25616
2
Revision 2.1
Jan.
2004
STC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage
Respect to GND
with
STC62WV25616
OPERATING RANGE
UNITS
V
O
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
-40
O
O
Vcc
2.4V ~ 5.5V
2.4V ~ 5.5V
C
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
C to +85
O
C
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
PARAMETER
NAME
V
IL
PARAMETER
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(2)
Input Leakage Current
Output Leakage Current
Output Low Voltage
TEST CONDITIONS
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
MIN. TYP.
(1)
MAX.
-0.5
2.0
2.2
--
--
--
2.4
2.4
--
--
--
--
--
0.8
0.8
Vcc+0.3
UNITS
V
V
IH
I
IL
I
LO
V
OL
--
V
uA
uA
V
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE = V
IH
, or OE,= V
IH
V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2.0mA
Vcc=3.0V
Vcc=5.0V
1
1
0.4
0.4
--
22
55
0.5
V
OH
(5)
Output High Voltage
Operating Power
Supply Current
Standby Current-TTL
(4)
Vcc = Min, I
OH
= -1.0mA
CE=V
IL
,I
DQ
= 0mA,
F=Fmax
(3)
Vcc=3.0V
Vcc=5.0V
--
V
I
CC
70ns
70ns
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
--
mA
I
CCSB
CE = V
IH
, I
DQ
= 0mA
Vcc=5.0V
--
Vcc=3.0V
Vcc=5.0V
--
0.45
2.0
mA
1.0
10
60
uA
I
CCSB1
Standby Current-CMOS
CE
≧
Vcc-0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦0.2V
--
1. Typical characteristics are at T
A
= 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
4. Icc
SB1_MAX.
is 5uA/30uA at Vcc=3.0V/5.0V and T
A
=70
o
C.
5. Icc_
MAX
. is 27mA(@3.0V)/65mA(@5.0V) under 55ns operation.
R0201-STC62WV25616
3
Revision 2.1
Jan.
2004
STC
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
(3)
STC62WV25616
TEST CONDITIONS
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
MIN. TYP.
1.5
--
0
T
RC (2)
--
0.3
--
--
(1)
MAX.
--
1.3
--
--
UNITS
V
uA
ns
ns
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. I
cc
DR
_
MAX.
is 0.8uA at T
A
=70
O
C.
LOW V
CC
DATA RETENTION WAVEFORM
( CE Controlled )
Data Retention Mode
Vcc
V
IH
Vcc
V
DR
≥
1.5V
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
R0201-STC62WV25616
4
Revision 2.1
Jan.
2004
STC
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
STC62WV25616
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
1V/ns
0.5Vcc
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
CYCLE TIME : 70ns
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
UNIT
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. TYP. MAX.
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
NOTE :
t
RC
t
AA
t
ACS
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
(1)
70
--
--
(LB,UB)
--
--
10
(LB,UB)
5
5
--
(LB,UB)
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
--
--
35
35
30
--
55
--
--
--
--
10
5
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
55
55
30
30
--
--
--
30
30
25
--
1. t
BA
is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; t
BA
is 70ns/55ns (@speed=70ns/55ns) without address toggle.
R0201-STC62WV25616
5
Revision 2.1
Jan.
2004
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