STD40NF3LL
N-channel 30V - 0.009Ω - 40A - DPAK
Low gate charge STripFET™ II Power MOSFET
General features
Type
STD40NF3LL
■
■
■
■
■
V
DSS
30V
R
DS(on)
<0.011Ω
I
D
40A
Logic level device
Optimal R
DS(on)
x Q
g
trade-off
Conduction losses reduced
Switching losses reduced
Low threshold drive
DPAK
3
1
Description
This application specific Power MOSFET is the
third generation of STMicroelectronics unique
"Single Feature Size™" strip-based process. The
resulting transistor shows the best trade-off
between on-resistance and gate charge. When
used as high and low side in buck regulators, it
gives the best performance in terms of both
conduction and switching losses. This is
extremely important for motherboards where fast
switching and high efficiency are of paramount
importance.
Internal schematic diagram
Applications
■
Switching application
Order codes
Part number
STD40NF3LLT4
Marking
D40NF3LL@
Package
DPAK
Packaging
Tape & reel
February 2007
Rev 5
1/13
www.st.com
13
Contents
STD40NF3LL
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
4
5
6
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
STD40NF3LL
Electrical ratings
1
Electrical ratings
Table 1.
Symbol
V
DS
V
DGR
V
GS
I
D(1)
I
D
I
DM(2)
P
tot
dv/dt
(3)
E
AS (4)
T
stg
T
j
Absolute maximum ratings
Parameter
Drain-source voltage (V
GS
= 0)
Drain-gate voltage (R
GS
= 20 kΩ)
Gate- source voltage
Drain current (continuous) at T
C
= 25°C
Drain current (continuous) at T
C
= 100°C
Drain current (pulsed)
Total dissipation at T
C
= 25°C
Derating Factor
Peak diode recovery voltage slope
Single pulse avalanche energy
Storage temperature
-55 to 175
Max. operating junction temperature
°C
Value
30
30
± 16
40
28
160
80
0.53
5.5
850
Unit
V
V
V
A
A
A
W
W/°C
V/ns
mJ
1. Current limited by package
2. Pulse width limited by safe operating area.
3. I
SD
≤
40A, di/dt
≤
350A/µs, V
DD
≤
V
(BR)DSS
, T
j
≤
T
JMAX
4. Starting T
j
= 25 °C, I
D
= 20A, V
DD
= 25V
Table 2.
Rthj-case
Rthj-amb
T
J
Thermal data
Thermal resistance junction-case max
Thermal resistance junction-ambient max
Maximum lead temperature for soldering purpose
1.88
100
300
°C/W
°C/W
°C
3/13
Electrical characteristics
STD40NF3LL
2
Electrical characteristics
(T
CASE
=25°C unless otherwise specified)
Table 3.
Symbol
V
(BR)DSS
On/off states
Parameter
Drain-source
breakdown voltage
Zero gate voltage
drain current (V
GS
= 0)
Gate-body leakage
current (V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
= 250µA, V
GS
=0
V
DS
= max rating
V
DS
= max rating,
T
C
= 125°C
V
GS
= ±16V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 20A
V
GS
= 4.5V, I
D
= 10A
1
0.0090
0.0115
0.0110
0.0135
Min.
30
1
10
±100
Typ.
Max.
Unit
V
µA
µA
nA
V
Ω
Ω
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Table 4.
Symbol
g
fs (1)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Dynamic
Parameter
Forward
transconductance
Input capacitance
Output capacitance
Reverse transfer
capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
V
DS
= 15V
,
I
D
= 20A
Min.
Typ.
23
1650
540
130
23
156
27
28
24
8.5
12
33
Max.
Unit
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
DS
= 25V, f = 1MHz,
V
GS
= 0
V
DD
= 15V, I
D
= 20A
R
G
= 4.7Ω V
GS
=4.5V
(see
Figure 13)
V
DD
=
15V, I
D
= 20A,
V
GS
= 4.5V, R
G
= 4.7Ω
(see
Figure 14)
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.
4/13
STD40NF3LL
Electrical characteristics
Table 5.
Symbol
I
SD
I
SDM
(1)
Source drain diode
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
I
SD
= 40A, V
GS
= 0
40
50
2.5
Test conditions
Min.
Typ.
Max.
40
160
1.3
Unit
A
A
V
ns
nC
A
V
SD (2)
t
rr
Q
rr
I
RRM
Reverse recovery time
I
SD
= 40A, di/dt = 100A/µs,
Reverse recovery charge V
DD
= 15V, T
j
= 150°C
Reverse recovery current (see
Figure 15)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
5/13
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