128Kx8 Autostore nvSRAM
FEATURES
• 25, 35, 45 ns Read Access & R/W Cycle Time
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware or Software
Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 200K STORE Cycles
• 20-Year Non-volatile Data Retention
• Single 3 V + 20%, -10% Power Supply
• Commercial and Industrial Temperatures
• Small Footprint SOIC & SSOP Packages (RoHS-
Compliant)
STK14CA8
DESCRIPTION
The Simtek STK14CA8 is a 1Mb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the
STORE
operation). On power up, data is automatically
restored to the SRAM (the
RECALL
operation). Both
STORE and RECALL operations are also available
under software control.
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
BLOCK DIAGRAM
Quantum Trap
1024 X 1024
ROW DECODER
STORE
STATIC RAM
ARRAY
1024 X 1024
RECALL
V
CC
V
CAP
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
15
– A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
11
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
Document Control #ML0022 Rev 1.5
February 2007
STK14CA8
PACKAGES
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
A
4
V
SS
48 Pin SSOP
Relative PCB area usage.
See website for detailed package
size specifications.
PIN DESCRIPTIONS
Pin Name
A
16
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
HSB
Input
I/O
Input
Input
Input
Power Supply
I/O
I/O
Description
Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 3.0V, +20%, -10%
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
Ground
Unlabeled pins have no internal connections.
V
CAP
V
SS
(Blank)
Power Supply
Power Supply
No Connect
Document Control #ML0022 Rev 1.5
February 2007
2
SSOP
DQ
0
A
3
A
2
A
1
A
0
DQ
1
DQ
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
A
15
HSB
W
A
13
A
8
A
9
A
11
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
HSB
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
6
G
A
10
E
DQ
7
DQ
5
DQ
4
DQ
3
V
CC
32 Pin SOIC
STK14CA8
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.1V
Voltage on Input Relative to V
SS
. . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB . . . . . . . . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .–55°C to 140°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS(V
CC
= 2.7V-
Package Thermal Characteristics - See Website at http://www.simtek.com
3.6V)
COMMERCIAL
SYMBOL
I
CC1
PARAMETER
MIN
Average V
CC
Current
65
55
50
70
60
55
mA
mA
mA
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
Dependent on output loading and cycle
rate. Values obtained without output
loads.
All Inputs Don’t Care, V
CC
= max
Average current for duration of STORE
cycle (t
STORE
)
W
≥
(V
CC
– 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output
loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (t
STORE
)
E
≥ (V
CC
-0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
-0.2V)
Standby current level after nonvolatile
cycle complete
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 2mA
I
OUT
= 4mA
MAX
MIN
MAX
INDUSTRIAL
UNITS
NOTES
I
CC2
Average V
CC
Current during
STORE
3
Average V
CC
Current at t
AVAV
= 200ns
3V, 25°C, Typical
10
10
mA
3
mA
I
CC3
I
CC4
Average V
CAP
Current during AutoStore
Cycle
V
CC
Standby Current
(Standby, Stable CMOS Levels)
3
3
3
3
mA
I
SB
mA
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
V
CC
V
CAP
NV
C
DATA
R
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
Storage Capacitance
Nonvolatile STORE operations
Data Retention
0
2.7
17
200
20
2.0
V
SS
–0.5
2.4
±1
±1
V
CC
+ 0.3
0.8
2.0
V
SS
–0.5
2.4
0.4
70
3.6
120
–40
2.7
17
200
20
±1
±1
V
CC
+ 0.3
0.8
μA
μA
V
V
V
0.4
85
3.6
120
V
°C
V
μF
K
Years
3.3V + 0.3V
Between V
CAP
pin and V
SS
, 5V rated.
@ 55 deg C
Note: The HSB pin has I
OUT
=-10 uA for V
OH
of 2.4 V, this parameter is characterized but not tested.
Document Control #ML0022 Rev 1.5
February 2007
3
STK14CA8
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2
CAPACITANCE
b
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
7
7
UNITS
pF
pF
CONDITIONS
ΔV
= 0 to 3V
ΔV
= 0 to 3V
Note b: These parameters are guaranteed but not tested.
3.0V
577 Ohms
OUTPUT
789 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1
:
AC Output Loading
3.0V
577 Ohms
OUTPUT
789 Ohms
5 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 2
:
AC Output Loading for Tristate Specs (t
HZ
, t
LZ
, t
WLQZ
, t
WHQZ
, t
GLQX
, t
GHQZ
)
Document Control #ML0022 Rev 1.5
February 2007
4
STK14CA8
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
1
2
3
4
5
6
7
8
9
10
11
t
AXQXd
t
AVAVc
t
AVQVd
#2
t
ELQV
t
AVAVc
t
AVQVd
t
GLQV
t
AXQXd
t
ELQX
t
EHQZe
t
GLQX
t
GHQZe
t
ELICCHb
t
EHICCLb
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
35
3
3
10
0
13
0
45
25
25
12
3
3
13
0
15
PARAMETER
MIN
MAX
25
35
35
15
3
3
15
MIN
MAX
35
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK14CA8-25
STK14CA8-35
STK14CA8-45
UNITS
Note c:
Note d:
Note e:
Note f:
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low
Measured
±
200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1:
Address Controlled
c,d,f
2
t
AVAV
ADDRESS
5
3
t
AVQV
DATA VALID
t
AXQX
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
c,f
2
t
AVAV
ADDRESS
6
t
ELQX
1
t
ELQV
11
t
EHICCL
7
t
EHQZ
E
G
8
t
GLQV
4
9
t
GHQZ
t
GLQX
DQ (DATA OUT)
DATA VALID
t
ELICCH
ACTIVE
10
I
CC
STANDBY
Document Control #ML0022 Rev 1.5
February 2007
5
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