STK11C48
2K x 8 nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
FEATURES
• 25ns, 35ns and 45ns Access Times
•
STORE
to Nonvolatile Elements Initiated by
Software
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention in Nonvolatile Ele-
ments
• Commercial and Industrial Temperatures
• 28-Pin 300 mil PDIP, 300 mil SOIC and
350 mil SOIC Packages
DESCRIPTION
The Simtek STK11C48 is a fast static
RAM
with a
nonvolatile element incorporated in each static
memory cell. The
SRAM
can be read and written an
unlimited number of times, while independent, non-
volatile data resides in the Nonvolatile Elements.
Data transfers from the
SRAM
to the Nonvolatile Ele-
ments (the
STORE
operation), or from Nonvolatile
Elements to
SRAM
(the
RECALL
operation), take
place using a software sequence. Transfers from the
Nonvolatile Elements to the
SRAM
(the
RECALL
operation) also take place automatically on restora-
tion of power.
BLOCK DIAGRAM
Quantum Trap
32 x 512
PIN CONFIGURATIONS
NC
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
A
6
A
7
A
8
A
9
STORE
STATIC RAM
ARRAY
32 x 512
RECALL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
- A
10
V
CC
W
NC
A
8
A
9
NC
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
ROW DECODER
28 - 300 PDIP
28 - 300 SOIC
28 - 350 SOIC
PIN NAMES
A
0
- A
10
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
DQ
0
- DQ
7
E
G
V
CC
V
SS
March 2006
1
Document Control # ML0003 rev 0.2
STK11C48
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC1b
PARAMETER
MIN
Average V
CC
Current
MAX
85
75
65
3
10
25
21
18
750
±1
±5
2.2
V
SS
– .5
2.4
0.4
0
70
–40
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
85
MIN
MAX
90
75
65
3
10
26
22
19
750
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
V
V
V
V
°C
INDUSTRIAL
UNITS
(V
CC
= 5.0V
±
10%)
NOTES
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
E
≥
(V
CC
- 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA
I
OUT
= 8mA
I
CC2c
I
CC3b
I
SB1d
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
I
SB2d
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC2
is the average current required for the duration of the
STORE
cycle (t
STORE
) .
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
480 Ohms
(T
A
= 25°C, f = 1.0MHz)
OUTPUT
MAX
8
7
UNITS
pF
pF
CONDITIONS
ΔV
= 0 to 3V
ΔV
= 0 to 3V
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
March 2006
2Document Control # ML0003 rev 0.2
STK11C48
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAVf
t
AVQVg
t
GLQV
t
AXQXg
t
ELQX
t
EHQZh
t
GLQX
t
GHQZh
t
ELICCHe
t
EHICCLd, e
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
35
5
5
10
0
13
0
45
25
25
10
5
5
13
0
15
MIN
MAX
25
35
35
15
5
5
15
MIN
MAX
35
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK11C48-25
(V
CC
= 5.0V + 10%)
STK11C48-35
STK11C48-45
UNITS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
f, g
t
AVAV
ADDRESS
5
t
AXQX
3
2
t
AVQV
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
f
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
7
6
1
2
t
EHICCL
11
G
4
t
GLQV
t
GHQZ
9
t
GLQX
DQ (DATA OUT)
t
ELICCH
I
CC
STANDBY
10
DATA VALID
8
ACTIVE
March 2006
3Document Control # ML0003 rev 0.2
STK11C48
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZh, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
MIN
25
20
20
10
0
20
0
0
10
5
MAX
MIN
35
25
25
12
0
25
0
0
13
5
MAX
MIN
45
30
30
15
0
30
0
0
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK11C48-25
(V
CC
= 5.0V + 10%)
STK11C48-35
STK11C48-45
UNITS
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1:
W Controlled
j
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
j
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
March 2006
4Document Control # ML0003 rev 0.2
STK11C48
STORE
INHIBIT/POWER-UP
RECALL
SYMBOLS
NO.
Standard
22
23
24
25
t
RESTORE
t
STORE
V
SWITCH
V
RESET
Power-up
RECALL
Duration
STORE
Cycle Duration
Low Voltage Trigger Level
Low Voltage Reset Level
4.0
PARAMETER
MIN
MAX
550
10
4.5
3.6
μs
ms
V
V
k
(V
CC
= 5.0V + 10%)
STK11C48
UNITS NOTES
Note k: t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
STORE
INHIBIT/POWER-UP
RECALL
V
CC
5V
24
V
SWITCH
25
V
RESET
STORE
INHIBIT
POWER-UP
RECALL
22
t
RESTORE
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
STORE
INHIBIT
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE
INHIBIT
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE
INHIBIT
RECALL
WHEN
V
CC
RETURNS
ABOVE V
SWITCH
March 2006
5Document Control # ML0003 rev 0.2
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
