TB67S109AFTG/FNG
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TB67S109AFTG, TB67S109AFNG
CLOCK-in controlled Bipolar Stepping Motor Driver
The TB67S109A is a two-phase bipolar stepping motor driver
using a PWM chopper. The clock in decoder is built in.
Fabricated with the BiCD process, rating is 50 V/4.0 A .
FTG
Features
•
BiCD process integrated monolithic IC.
•
Capable of controlling 1 bipolar stepping motor.
•
PWM controlled constant-current drive.
•
Allows full, half, quarter, 1/8, 1/16, 1/32 step operation.
•
Low on-resistance (High + Low side=0.49Ω(typ.)) MOSFET
output stage.
•
High efficiency motor current control mechanism (Advanced
Dynamic Mixed Decay)
•
High voltage and current (For specification, please refer to absolute
maximum ratings and operation ranges)
•
Error detection (TSD/ISD) signal output function
•
Built-in error detection circuits (Thermal shutdown (TSD), over-current
shutdown (ISD), and power-on reset (POR))
•
Built-in VCC regulator for internal circuit use.
•
Chopping frequency of a motor can be customized by external resistance and capacitor.
•
Multi package lineup
TB67S109AFTG: P-WQFN48-0707-0.50-003
TB67S109AFNG: HTSSOP48-P-300-0.50
Note) Please be careful about
thermal conditions during use.
HTSSOP48-P-300-0.50
Weight 0.21g (typ.)
P-WQFN48-0707-0.50-003
Weight 0.10g (typ.)
FNG
© 2014-2020
Toshiba Electronic Devices & Storage Corporation
1
2020-2-4
TB67S109AFTG/FNG
Pin assignment (TB67S109A)
(Top View)
OUTB+
OUTB+
OUTA+
VCC
RSB
RSB
VM
NC
NC
NC
NC
36 35 34 33 32 31 30 29 28 27 26 25
NC
LO
DMODE0
GND
VREFB
VREFA
OSCM
CW/CCW
MO
DMODE1
DMODE2
NC
37
38
39
40
41
42
43
44
45
46
47
48
1
NC
2
CLK
3
ENABLE
4
RESET
5
GND
6
NC
7
RSA
8
RSA
9 10 11 12
OUTA+
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FTG
24 NC
23 NC
22 GND
21 OUTB-
20 OUTB-
19 GND
18 GND
17 OUTA-
16 OUTA-
15 GND
14 NC
13 NC
Please solder the four corner pins of the QFN package and the exposed pad to the GND area of the PCB.
(Top View)
OSCM
NC
CW/CCW
MO
DMODE1
NC
DMODE2
CLK
ENABLE
RESET
GND
NC
RSA
RSA
NC
OUTA+
OUTA+
NC
NC
GND
NC
OUTA-
OUTA-
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VREFA
VREFB
GND
DMODE0
LO
NC
NC
VCC
NC
VM
NC
NC
RSB
RSB
NC
OUTB+
OUTB+
NC
NC
GND
NC
OUTB-
OUTB-
GND
NC
FNG
Please solder the exposed pad of the HTSSOP package to the GND area of the PCB.
2
NC
2020-2-4
TB67S109AFTG/FNG
Application Notes
When using TB67S109A, the GND pattern of PCB should be a solid pattern and be externally terminated at only
one point. Also, a grounding method should be considered for efficient heat dissipation.
Careful attention should be paid to the layout of the output, VDD(VM) and GND traces, to avoid short circuits
across output pins or to the power supply or ground. If such a short circuit occurs, the device may be permanently
damaged.
Also, the utmost care should be taken for pattern designing and implementation of the device since it has power
supply pins (VM, RS, OUT, GND) through which a particularly large current may run. If these pins are wired
incorrectly, an operation error may occur or the device may be destroyed.
The logic input pins must also be wired correctly. Otherwise, the device may be damaged owing to a current running
through the IC that is larger than the specified current.
4
2020-2-4
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