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SY100E111JITR

产品描述1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE
产品类别逻辑    逻辑   
文件大小93KB,共4页
制造商Microchip(微芯科技)
官网地址https://www.microchip.com
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SY100E111JITR概述

1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE

SY100E111JITR规格参数

参数名称属性值
厂商名称Microchip(微芯科技)
零件包装代码QLCC
包装说明LCC-28
针数28
Reach Compliance Codecompli
系列100E
输入调节DIFFERENTIAL
JESD-30 代码S-PQCC-J28
长度11.48 mm
逻辑集成电路类型LOW SKEW CLOCK DRIVER
功能数量1
反相输出次数
端子数量28
实输出次数18
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装形状SQUARE
封装形式CHIP CARRIER
传播延迟(tpd)0.73 ns
Same Edge Skew-Max(tskwd)0.05 ns
座面最大高度4.57 mm
表面贴装YES
技术ECL
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
宽度11.48 mm

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NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc.
1:9 DIFFERENTIAL CLOCK
DRIVER WITH ENABLE
SY10E111
SY100E111
SY10E111
SY100E111
FEATURES
s
s
s
s
Low skew
Extended 100E V
EE
range of –4.2V to –5.5V
Guaranteed skew limits
Differential design
DESCRIPTION
The SY10/100E111 are low skew 1-to-9 differential
drivers designed for clock distribution in new, high-
performance ECL systems. They accept one differential or
single-ended input, with V
BB
used for single-ended
operation. The signal is fanned out to nine identical
differential outputs. An enable input is also provided such
that a logic HIGH disables the device by forcing all Q
outputs LOW and all /Q outputs HIGH.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the E111 shares a common set of “basic”
processing with the other members of the ECLinPS™
family, wafer characterization at the point of device
personalization allows for tighter control of parameters,
including propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
The V
BB
output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using V
BB
for this purpose, it is
recommended that V
BB
is decoupled to V
CC
via a 0.01µF
capacitor.
s
V
BB
output
s
Enable input
s
Fully compatible with industry standard 10KH, 100K
I/O levels
s
75K
input pulldown resistors
s
Fully compatible with ON Semiconductor
MC10E/100E111
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
IN
IN
EN
Q
5
Q
6
Q
4
Q
4
Q
5
PIN NAMES
Pin
Function
Differential Input Pair
Enable Input
Differential Outputs
V
BB
Output
V
CC
to Output
Q
6
Q
7
Q
7
Q
8
V
BB
Q
8
IN, /IN
/EN
Q0, /Q0 — Q8, /Q8
V
BB
V
CCO
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: March 2006

 
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