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SY100E111LJI

产品描述5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE)
产品类别逻辑    逻辑   
文件大小74KB,共6页
制造商Microchip(微芯科技)
官网地址https://www.microchip.com
下载文档 详细参数 全文预览

SY100E111LJI概述

5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE)

SY100E111LJI规格参数

参数名称属性值
厂商名称Microchip(微芯科技)
包装说明QCCJ,
Reach Compliance Codecompli
系列100E
输入调节DIFFERENTIAL
JESD-30 代码S-PQCC-J28
长度11.48 mm
逻辑集成电路类型LOW SKEW CLOCK DRIVER
功能数量1
反相输出次数
端子数量28
实输出次数18
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装形状SQUARE
封装形式CHIP CARRIER
传播延迟(tpd)0.78 ns
Same Edge Skew-Max(tskwd)0.075 ns
座面最大高度4.57 mm
表面贴装YES
技术ECL
温度等级INDUSTRIAL
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
宽度11.48 mm

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Micrel, Inc.
5V/3.3V 1:9 DIFFERENTIAL
CLOCK DRIVER (w/o ENABLE)
Precison Edge
®
SY10E111A/L
Precision Edge
®
SY100E111A/L
SY10E111A/L
SY100E111A/L
FEATURES
s
s
s
s
s
s
5V and 3.3V power supply options
200ps part-to-part skew
50ps output-to-output skew
Differential design
V
BB
output
Voltage and temperature compensated outputs
Precision Edge
®
DESCRIPTION
The SY10/100E111A/L are low skew 1-to-9 differential
driver designed for clock distribution in mind. The
SY10/100E111A/L's function and performance are similar to
the popular SY10/100E111, with the improvement of lower
jitter and the added feature of low voltage operation. It accepts
one signal input, which can be either differential or single-
ended if the V
BB
output is used. The signal is fanned out to 9
identical differential outputs.
The E111A/L are specifically designed, modeled and
produced with low skew as the key goal. Optimal design and
layout serve to minimize gate to gate skew within a device, and
empirical modeling is used to determine process control limits
that ensure consistent t
pd
distributions from lot to lot. The net
result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used. In
most applications, all nine differential pairs will be used and
therefore terminated. In the case where fewer that nine pairs
are used, it is necessary to terminate at least the output pairs
on the same package side as the pair(s) being used on that
side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order
of 10-20ps) of the output(s) being used which, while not being
catastrophic to most designs, will mean a loss of skew margin.
The E111A/L, as with most other ECL devices, can be
operated from a positive V
CC
supply in PECL mode. This
allows the E111A/L to be used for high performance clock
distribution in +5V/+3.3V systems. Designers can take
advantage of the E111A/L's performance to distribute low
skew clocks across the backplane or the board. In a PECL
environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For
systems incorporating GTL, parallel termination offers the
lowest power by taking advantage of the 1.2V supply as
terminating voltage.
s
75K
input pulldown resistors
s
Fully compatible with Motorola MC100LVE111
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
IN
IN
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
V
BB
Q
8
PIN NAMES
Pin
IN, IN
Q
0
, Q
0
— Q
8
, Q
8
V
BB
V
CCO
Function
Differential Input Pair
Differential Outputs
V
BB
Output
V
CC
to Output
Precision Edge is a registered trademark of Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: J
Amendment: /0
March 2006
1
Rev. Date:

 
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