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SY100E137JZTR: 产品描述8-BIT RIPPLE COUNTER; 产品类别逻辑逻辑; 文件大小65KB，共5页; 制造商Microchip(微芯科技); 官网地址https://www.microchip.com; 标准

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SY100E137JZTR概述

8-BIT RIPPLE COUNTER

SY100E137JZTR规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	Microchip(微芯科技)
零件包装代码	QLCC
包装说明	QCCJ, LDCC28,.5SQ
针数	28
Reach Compliance Code	compli
计数方向	UP
系列	100E
JESD-30 代码	S-PQCC-J28
JESD-609代码	e3
长度	11.48 mm
负载/预设输入	NO
逻辑集成电路类型	BINARY COUNTER
最大频率@ Nom-Su	1800000000 Hz
工作模式	ASYNCHRONOUS
湿度敏感等级	2
位数	8
功能数量	1
端子数量	28
最高工作温度	85 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	QCCJ
封装等效代码	LDCC28,.5SQ
封装形状	SQUARE
封装形式	CHIP CARRIER
包装方法	TAPE AND REEL
峰值回流温度（摄氏度）	260
电源	-4.5 V
最大电源电流（ICC）	167 mA
传播延迟（tpd）	4.8 ns
认证状态	Not Qualified
座面最大高度	4.57 mm
表面贴装	YES
技术	ECL
温度等级	OTHER
端子面层	Matte Tin (Sn)
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	40
触发器类型	POSITIVE EDGE
宽度	11.48 mm
最小 fmax	1800 MHz

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Micrel, Inc.

8-BIT RIPPLE

COUNTER

SY10E137

SY100E137

SY10E137

SY100E137

FEATURES

1.8GHz min. count frequency

Extended 100E V

range of –4.2V to –5.5V

Synchronous and asynchronous enable pins

Differential clock input and data output pins

output for single-ended use

Asynchronous Master Reset

DESCRIPTION

The SY10/100E137 are very high speed binary ripple

counters. The two least significant bits were designed

with very fast edge rates, while the more significant bits

maintain standard ECLinPS output edge rates. This allows

the counters to operate at very high frequencies, while

maintaining a moderate power dissipation level.

The devices are ideally suited for multiple frequency

clock generation, as well as for counters in high-

performance ATE time measurement boards.

Both asynchronous and synchronous enables are

available to maximize the device's flexibility for various

applications. The asynchronous enable input, A_Start,

when asserted, enables the counter while overriding any

synchronous enable signals. The E137 features XOR'ed

enable inputs, EN

and EN

, which are synchronous to

the CLK input. When only one synchronous enable is

asserted, the counter becomes disabled on the next CLK

transition. All outputs remain in the previous state poised

for the other synchronous enable or A_Start to be

asserted in order to re-enable the counter. Asserting

both synchronous enables causes the counter to become

enabled on the next transition of the CLK. EN

(or EN

)

and CLK edges are coincident. Sufficient delay has been

inserted in the CLK path (to compensate for the XOR

gate delay and the internal D-flip-flop set-up time) to

ensure that the synchronous enable signal is clocked

correctly; hence, the counter is disabled.

The E137 can also be driven single-endedly utilizing

the V

output supply as the voltage reference for the

CLK input signal. If a single-ended signal is to be used,

the V

pin should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. V

can

only source/sink 0.5mA; therefore, it should be used as

a switching reference for the E137 only.

All input pins left open will be pulled LOW via an input

pull-down resistor. Therefore, do not leave the differential

CLK inputs open. Doing so causes the current source

transistor of the input clock gate to become saturated,

thus upsetting the internal bias regulators and

jeopardizing the stability of the device.

The asynchronous Master Reset resets the counter to

an all zero state upon assertion.

Internal 75K

Ω

input pull-down resistors

Available in 28-pin PLCC packge

PIN NAMES

CLK, CLK

–Q

, Q

–Q

A_Start

, EN

CCO

Function

Differential Clock Inputs

Differential Q Outputs

Asynchronous Enable Input

Synchronous Enable Inputs

Asynchronous Master Reset

Switching Reference Output

to Output

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: E

Amendment: /0

Issue Date: March 2006

SY100E137JZTR相似产品对比

	SY100E137JZTR	SY100E137	SY10E137	SY10E137JC	SY10E137_06	SY10E137JZTR	SY10E137JCTR	SY100E137JCTR	SY100E137JC
描述	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER
是否Rohs认证	符合	-	-	不符合	-	符合	不符合	不符合	-
厂商名称	Microchip(微芯科技)	-	-	Microchip(微芯科技)	-	Microchip(微芯科技)	Microchip(微芯科技)	Microchip(微芯科技)	-
包装说明	QCCJ, LDCC28,.5SQ	-	-	QCCJ, LDCC28,.5SQ	-	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ	-
Reach Compliance Code	compli	-	-	_compli	-	compli	_compli	_compli	-
计数方向	UP	-	-	UP	-	UP	UP	UP	-
系列	100E	-	-	10E	-	10E	10E	100E	-
JESD-30 代码	S-PQCC-J28	-	-	S-PQCC-J28	-	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28	-
JESD-609代码	e3	-	-	e0	-	e3	e0	e0	-
负载/预设输入	NO	-	-	NO	-	NO	NO	NO	-
逻辑集成电路类型	BINARY COUNTER	-	-	BINARY COUNTER	-	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	-
最大频率@ Nom-Su	1800000000 Hz	-	-	1800000000 Hz	-	1800000000 Hz	1800000000 Hz	1800000000 Hz	-
工作模式	ASYNCHRONOUS	-	-	ASYNCHRONOUS	-	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	-
位数	8	-	-	8	-	8	8	8	-
功能数量	1	-	-	1	-	1	1	1	-
端子数量	28	-	-	28	-	28	28	28	-
最高工作温度	85 °C	-	-	85 °C	-	85 °C	85 °C	85 °C	-
封装主体材料	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
封装代码	QCCJ	-	-	QCCJ	-	QCCJ	QCCJ	QCCJ	-
封装等效代码	LDCC28,.5SQ	-	-	LDCC28,.5SQ	-	LDCC28,.5SQ	LDCC28,.5SQ	LDCC28,.5SQ	-
封装形状	SQUARE	-	-	SQUARE	-	SQUARE	SQUARE	SQUARE	-
封装形式	CHIP CARRIER	-	-	CHIP CARRIER	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	-
电源	-4.5 V	-	-	-5.2 V	-	-5.2 V	-5.2 V	-4.5 V	-
最大电源电流（ICC）	167 mA	-	-	145 mA	-	145 mA	145 mA	167 mA	-
传播延迟（tpd）	4.8 ns	-	-	4.8 ns	-	4.8 ns	4.8 ns	4.95 ns	-
认证状态	Not Qualified	-	-	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	-
表面贴装	YES	-	-	YES	-	YES	YES	YES	-
技术	ECL	-	-	ECL	-	ECL	ECL	ECL	-
温度等级	OTHER	-	-	OTHER	-	OTHER	OTHER	INDUSTRIAL	-
端子面层	Matte Tin (Sn)	-	-	Tin/Lead (Sn85Pb15)	-	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	-
端子形式	J BEND	-	-	J BEND	-	J BEND	J BEND	J BEND	-
端子节距	1.27 mm	-	-	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm	-
端子位置	QUAD	-	-	QUAD	-	QUAD	QUAD	QUAD	-
触发器类型	POSITIVE EDGE	-	-	POSITIVE EDGE	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	-
最小 fmax	1800 MHz	-	-	1800 MHz	-	1800 MHz	1800 MHz	2200 MHz	-

SY100E137JZTR

SY100E137JZTR概述

SY100E137JZTR规格参数

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SY100E137JZTR相似产品对比

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