NOT RECOMMENDED FOR NEW DESIGNS
6-BIT 2:1
MUX-LATCH
FEATURES
750ps max. LEN to output
Extended 100E V
EE
range of –4.2V to –5.5V
700ps max. D to output
Single-ended outputs
Asynchronous Master Reset
Dual latch-enables
Fully compatible with industry standard 10KH,
100K ECL levels
Internal 75K
Ω
input pulldown resistors
Fully compatible with Motorola MC10E/100E155
Available in 28-pin PLCC package
SY10E155
SY100E155
FINAL
DESCRIPTION
The SY10/100E155 offer six 2:1 multiplexers followed
by latches with single-ended outputs, designed for use in
new, high-performance ECL systems. The two external
latch-enable signals (LEN
1
and LEN
2)
are gated through a
logical OR operation before use as control for the six
latches. When both LEN
1
and LEN
2
are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN
1
or LEN
2
(or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL (Select)
signal which selects one of the two bits of input data at each
mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
BLOCK DIAGRAM
D
0a
D
0b
D
1a
D
1b
D
2a
D
2b
D
3a
D
3b
D
4a
D
4b
D
5a
D
5b
SEL
LEN
1
LEN
2
MR
MUX
SEL
D
E
N R
D
E
NR
D
E
NR
D
E
NR
D
E
NR
D
E
NR
Q
Q
5
Q
Q
4
Q
Q
3
Q
Q
2
Q
Q
1
Q
Q
0
PIN CONFIGURATION
D
3a
NC
V
CCO
D
5a
D
4b
25 24 23 22 21 20 19
D
5b
LEN
1
LEN
2
V
EE
MR
SEL
D
0b
D
4a
D
3b
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
MUX
SEL
Q
5
Q
4
V
CC
Q
3
Q
2
V
CCO
Q
1
PLCC
TOP VIEW
J28-1
16
15
14
13
12
MUX
SEL
V
CCO
D
0b
D
1a
D
1b
D
2a
D
2b
MUX
SEL
MUX
SEL
PIN NAMES
Pin
D
0a
–D
5a
D
0b
–D
5b
SEL
LEN
1
, LEN
2
MR
Q
0
–Q
5
V
CCO
Function
Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
Outputs
V
CC
to Output
MUX
SEL
Q
0
Rev.:
D
Amendment: /1
REV:
C
Issue
Date:
September 2011
Date:
February, 1998
Issue
1
Micrel
SY10E155
SY100E155
TRUTH TABLES
SEL
H
L
Data
a
b
LEN
1
L
H
X
LEN
2
L
X
H
Latch
Transparent
Latched
Latched
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
°
C
Symbol
I
IH
I
EE
Parameter
Input HIGH Current
Power Supply Current
10E
100E
Min.
—
—
—
—
85
85
150
102
102
T
A
= +25
°
C
Max.
150
102
102
—
—
—
—
85
85
T
A
= +85
°
C
Min. Typ.
—
—
—
—
85
98
Max.
150
102
117
Unit
µA
mA
Condition
—
—
Typ. Max. Min. Typ.
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
°
C
Symbol
t
PLH
t
PHL
Parameter
Min.
Propagation Delay to Output
D
325
SEL
475
LEN
350
MR
450
Set-up Time
D
SEL
Hold Time
D
SEL
Reset Recovery Time
Minimum Pulse Width, MR
Within-Device Skew
Rise/Fall Time
20% to 80%
300
500
300
0
800
400
—
300
T
A
= +25
°
C
Max.
700
925
750
850
—
—
—
—
—
—
—
800
T
A
= +85
°
C
Min. Typ.
325
475
350
450
300
500
300
0
800
400
—
300
500
675
500
600
100
250
–100
–250
650
—
75
450
Max.
700
925
750
850
—
—
—
—
—
—
—
800
Unit
ps
Condition
—
Typ. Max. Min. Typ.
500
675
500
600
100
250
–100
–250
650
—
75
450
700
925
750
850
—
—
—
—
—
—
—
800
325
475
350
450
300
500
300
0
800
400
—
300
500
675
500
600
100
250
–100
–250
650
—
75
450
t
S
ps
—
t
H
ps
—
t
RR
t
PW
t
skew
t
r
t
f
ps
ps
ps
ps
—
—
1
—
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering
Code
SY10E155JZ
SY10E155JZTR
SY100E155JZ
SY100E155JZTR
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
2
Micrel
SY10E155
SY100E155
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4
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