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SY100E160JZ

产品描述12-BIT PARITY GENERATOR/CHECKER
产品类别逻辑    逻辑   
文件大小60KB,共5页
制造商Microchip(微芯科技)
官网地址https://www.microchip.com
下载文档 详细参数 全文预览

SY100E160JZ概述

12-BIT PARITY GENERATOR/CHECKER

SY100E160JZ规格参数

参数名称属性值
厂商名称Microchip(微芯科技)
零件包装代码QLCC
包装说明QCCJ,
针数28
Reach Compliance Codeunknow
系列100E
JESD-30 代码S-PQCC-J28
JESD-609代码e3
长度11.48 mm
逻辑集成电路类型PARITY GENERATOR/CHECKER
位数12
功能数量1
端子数量28
最高工作温度85 °C
最低工作温度
输出极性COMPLEMENTARY
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装形状SQUARE
封装形式CHIP CARRIER
传播延迟(tpd)0.95 ns
认证状态Not Qualified
座面最大高度4.57 mm
表面贴装YES
技术ECL
温度等级COMMERCIAL EXTENDED
端子面层MATTE TIN
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
宽度11.48 mm

文档预览

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Micrel, Inc.
12-BIT PARITY
GENERATOR/CHECKER
SY10E160
SY100E160
SY10E160
SY100E160
FEATURES
s
Provides odd-HIGH parity of 12 inputs
s
Extended 100E V
EE
range of –4.2V to –5.5V
s
s
s
s
Output register with Shift/Hold capability
900ps max. D to Q, /Q output
Enable control
Asynchronous Register Reset
DESCRIPTION
The SY10/100E160 are high-speed, 12-bit parity
generator/checkers with differential outputs, for use in
new, high-performance ECL systems. The output Q takes
on a logic HIGH value only when an odd number of inputs
are at a logic HIGH. A logic HIGH on the enable input (EN)
forces the output Q to a logic LOW.
An additional feature of the E160 is the output register.
Two multiplexers and their associated signals control the
register input by providing the option of holding present
data, loading the new parity data or shifting external data
in. To hold the present data, the Hold signal (HOLD) must
be at a logic LOW level. If the HOLD signal is at a logic
HIGH, the data present at the Q output is passed through
the first multiplexer. Taking the Shift signal (SHIFT) to a
logic HIGH will shift the data at the S-IN pin into the output
register. If the SHIFT signal is at a logic LOW, the output
of the first multiplexer is then passed through to the register.
The register itself is clocked on the rising edge of CLK
1
or CLK
2
(or both). The presence of a logic HIGH on the
reset pin (R) forces the register output Y to a logic LOW.
s
Differential outputs
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E160
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
EN
HOLD
S-IN
SHIFT
CLK
1
CLK
2
R
Q
Q
0
MUX
1
SEL
1
SEL
R
0
MUX
Y
D
Y
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: F
Amendment: /0
1
Issue Date: March 2006

 
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