NOT RECOMMENDED FOR NEW DESIGNS
SEMICONDUCTOR
SYNERGY
6-BIT 2:1 MUX-REGISTER
SY10E167
SY100E167
SY10E167
SY100E167
FEATURES
s
s
s
s
s
s
1000MHz min. operating frequency
Extended 100E V
EE
range of –4.2V to –5.5V
800ps max. clock to output
Single-ended outputs
Asynchronous Master Reset
Dual clocks
DESCRIPTION
The SY10/100E167 offer six 2:1 multiplexers followed
by D flip-flops with single-ended outputs, designed for use
in new, high-performance ECL systems. The Select (SEL)
control allows one of the two data inputs to the multiplexer
to pass through. The two external clock signals (CLK
1
,
CLK
2
) are gated through a logical OR operation before use
as control for the six flip-flops. The selected data are
transferred to the flip-flops on the rising edge of CLK
1
or
CLK
2
(or both).
The multiplexer operation is controlled by the Select
(SEL) signal which selects one of the two bits of input data
at each mux to be passed through.
When a logic HIGH is applied to the Master Reset (MR)
signal, it operates asychronously to take all outputs Q to a
logic LOW.
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
Ω
input pulldown resistors
s
ESD protection of 2000V
s
Fully compatible with Motorola MC10E/100E167
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
D
0a
MUX
D
0b
D
1a
MUX
D
1b
D
2a
MUX
D
2b
D
3a
MUX
D
3b
D
4a
MUX
D
4b
D
5a
MUX
D
5b
SEL
CLK
1
CLK
2
MR
SEL
SEL
D
R
SEL
D
R
Q
Q
5
SEL
D
R
Q
Q
4
SEL
D
R
Q
Q
3
SEL
D
R
Q
Q
2
D
R
Q
Q
0
PIN CONFIGURATION
D
3b
D
3a
NC
V
CCO
D
5a
D
5b
CLK
1
CLK
2
V
EE
MR
SEL
D
0a
25 24 23 22 21 20 19
D
4b
D
4a
Q
Q
1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
5
Q
4
V
CC
Q
3
Q
2
V
CCO
Q
1
TOP VIEW
PLCC
J28-1
16
15
14
13
12
D
0b
D
1a
D
1b
PIN NAMES
Pin
D
0a
–D
5a
D
0b
–D
5b
SEL
CLK
1
, CLK
2
MR
Q
0
–Q
5
V
CCO
Function
Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs
V
CC
to Output
Rev.: C
Amendment: /1
© 1999 Micrel-Synergy
5-127
V
CCO
Q
0
Issue Date: February, 1998
D
2a
D
2b
SEMICONDUCTOR
SYNERGY
SY10E167
SY100E167
TRUTH TABLE
SEL
H
L
Data
a
b
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
°
C
Symbol
I
IH
I
EE
Parameter
Input HIGH Current
Power Supply Current
10E
100E
—
—
94
94
113
113
—
—
94
94
113
113
—
—
94
108
113
130
—
—
150
T
A
= +25
°
C
—
—
150
T
A
= +85
°
C
Max.
150
Unit
µA
mA
Condition
—
—
—
—
Min. Typ. Max. Min. Typ.
Max. Min. Typ.
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
°
C
Symbol
f
MAX
t
PLH
t
PHL
t
S
Parameter
Max. Toggle Frequency
Propagation Delay to Output
CLK
MR
Set-up Time
D
SEL
Hold Time
D
SEL
Reset Recovery Time
Minimum Pulse Width
CLK, MR
Within-Device Skew
Rise/Fall Time
20% to 80%
1000 1400
450
450
100
275
300
75
750
400
—
300
650
650
–50
125
50
–125
550
—
75
450
—
800
850
—
—
—
—
—
—
—
800
T
A
= +25
°
C
1000 1400
450
450
100
275
300
75
750
400
—
300
650
650
–50
125
50
–125
550
—
75
450
—
800
850
—
—
—
—
—
—
—
800
T
A
= +85
°
C
Max.
—
800
850
ps
100
275
300
75
750
400
—
300
–50
125
50
–125
550
—
75
450
—
—
ps
—
—
—
—
—
800
ps
ps
ps
ps
—
—
1
—
—
—
Unit
MHz
ps
450
450
650
650
Condition
—
—
1000 1400
Min. Typ. Max. Min. Typ.
Max. Min. Typ.
t
H
t
RR
t
PW
t
skew
t
r
t
f
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering
Code
SY10E167JC
SY10E167JCTR
SY100E167JC
SY100E167JCTR
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
5-128
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