(PDCs) designed primarily for clock de-skewing and timing
adjustment. They provide variable delay of a differential
ECL input transition.
The delay section consists of a chain of gates
organized as shown in the logic diagram. The first two
delay elements feature gates that have been modified to
have delays 1.25 and 1.5 times the basic gate delay of
approximately 80ps. These two elements provide the
E195 with a digitally-selectable resolution of
approximately 20ps. The required device delay is selected
by the seven address inputs D[0:6], which are latched
on-chip by a high signal on the latch enable (LEN) control.
If the LEN signal is either LOW or left floating, then the
latch is transparent.
Because the delay programmability of the E195 is
achieved by purely differential ECL gate delays, the
device will operate at frequencies of >1GHz, while
maintaining over 600mV of output swing.
The E195 thus offers very fine resolution, at very high
frequencies, selectable entirely from a digital input,
allowing for very accurate system clock timing.
An eighth latched input, D
7
, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
≈
20ps/digital step resolution
>1GHz bandwidth
On-chip cascade circuitry
75Kk
Ω
input pulldown resistor
s
Fully compatible with Motorola MC10E/100E195
s
Available in 28-pin PLCC package
PIN NAMES
Pin
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
Function
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Minimum Delay Set
Maximum Delay Set
Cascade Signal
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: H
Amendment: /0
1
Issue Date: March 2006
Micrel, Inc.
Precison Edge
®
SY10E195
SY100E195
PACKAGE/ORDERING INFORMATION
D
7
NC
D
2
D
3
D
4
D
5
D
6
Ordering Information
(1)
Part Number
18
17
25 24 23 22 21 20 19
Package
Type
J28-1
J28-1
J28-1
J28-1
J28-1
J28-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Industrial
Package
Marking
SY10E195JC
SY10E195JC
SY100E195JI
SY100E195JI
SY10E195JZ with
Pb-Free bar-line indicator
SY10E195JZ with
Pb-Free bar-line indicator
SY100E195JY with
Pb-Free bar-line indicator
SY100E195JY with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Matte-Sn
Matte-Sn
Matte-Sn
Matte-Sn
D
1
D
0
LEN
V
EE
IN
IN
V
BB
26
27
28
1
2
3
4
5
6
7
8
9
10 11
NC
NC
V
CC
V
CCO
Q
Q
V
CCO
SY10E195JC
SY10E195JCTR
(2)
SY100E195JI
SY100E195JITR
(2)
SY10E195JZ
(3)
SY10E195JZTR
(2, 3)
TOP VIEW
PLCC
J28-1
16
15
14
13
12
EN
SET MIN
SET MAX
NC
NC
CASCADE
CASCADE
SY100E195JY
(3)
SY100E195JYTR
(2, 3)
28-Pin PLCC (J28-1)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precison Edge
®
SY10E195
SY100E195
BLOCK DIAGRAM
V
BB
EN
IN
IN
SET MAX
SET MIN
LEN
*1.25
*1.5
1
0
1
1
D
0
D
1
D
2
7-Bit Latch
D
3
D
4
D
5
D
6
Q
LEN
Latch
D
D
7
Cascade
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
4 gates
0
8 gates
0
16 gates
0
*Delays are 25% or 50% longer than
standard (standard = 80ps).
Q
Q
CASCADE
CASCADE
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precison Edge
®
SY10E195
SY100E195
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= GND
T
A
= 0
°
C
Symbol
I
IH
I
EE
Parameter
Input HIGH Current
Power Supply Current
10E
100E
—
—
130
130
156
156
—
—
130
130
156
156
—
—
130
150
156
179
Min.
—
Typ.
—
Max.
150
Min.
—
T
A
= +25
°
C
Typ.
—
Max.
150
—
T
A
= +85
°
C
Min.
Typ.
—
Max.
150
Unit
µA
mA
Condition
—
—
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precison Edge
®
SY10E195
SY100E195
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= GND
T
A
= 0
°
C
Symbol
t
PD
Parameter
Propagation Delay to Output
IN to Q; Tap = 0
IN to Q; Tap = 127
EN to Q; Tap = 0
D
7
to CASCADE
Programmable Range
t
PD
(max.) – t
PD
(min.)
Step Delay
D
0
High
D
1
High
D
2
High
D
3
High
D
4
High
D
5
High
D
6
High
Linearity
Duty Cycle Skew, t
PHL
–t
PLH
Set-up Time
D to LEN
D to IN
EN to IN
Hold Time
LEN to D
IN to EN
Release Time
EN to IN
SET MAX to LEN
SET MIN to LEN
Jitter
Rise/Fall Times
20–80% (Q)
20–80% (CASCADE)
Min.
1210
3320
1250
300
2000
Typ.
1360
3570
1450
450
2175
Max.
1510
3820
1650
700
—
T
A
= +25
°
C
Min.
1240
3380
1275
300
2050
Typ.
1390
3630
1475
450
2240
Max.
1540
3880
1675
700
—
T
A
= +85
°
C
Min.
1440
3920
1350
300
2375
Typ.
1590
4270
1650
450
2580
Max. Unit
ps
1765
4720
1950
700
—
ps
ps
—
—
55
115
250
505
1000
D
1
—
200
800
200
500
0
300
800
800
—
125
300
17
34
68
136
272
544
1088
D
0
±30
0
—
—
250
—
—
—
—
<5
225
450
—
—
105
180
325
620
1190
—
—
—
—
—
—
—
—
—
—
—
325
650
—
—
55
115
250
515
1030
D
1
—
200
800
200
500
0
300
800
800
—
125
300
17.5
35
70
140
280
560
1120
D
0
±30
0
—
—
250
—
—
—
—
<5
225
450
—
—
105
180
325
620
1220
—
—
—
—
—
—
—
—
—
—
—
325
650
—
—
65
140
305
620
1240
D
1
—
200
800
200
500
0
300
800
800
—
125
300
21
42
84
168
336
672
1344
D
0
±30
0
—
—
250
—
—
—
—
<5
225
450
—
—
120
205
380
740
1450
—
—
—
—
—
ps
—
—
ps
—
—
—
—
325
650
ps
ps
5
4
—
ps
ps
2
3
7
1
—
6
Condition
—
t
RANGE
∆t
Lin
t
skew
t
S
t
H
t
R
t
jit
t
r
t
f
8
—
Notes:
2. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
3. This set-up time defines the amount of time prior to the input signal the delay tap of the device must be set.
4. This set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75mV
to
that IN/IN transition.
5. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than
±75mV
to that IN/IN transition.
6. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified
IN to Q propagation delay and transition times.
7. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay
control inputs will typically realize D
0
resolution steps across the specified programmable range.
8. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing
binary counts on the control inputs D
n
). Typically, the device will be monotonic to the D
0
input, however, under worst case conditions and process variation,
delays could decrease slightly with increasing binary counts when the D
0
input is the LSB. With the D
1
input as the LSB, the device is guaranteed to be
monotonic over all specified environmental conditions and process variation.
9. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
