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SY100E196JITR: 产品描述PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT; 产品类别逻辑逻辑; 文件大小110KB，共10页; 制造商Microchip(微芯科技); 官网地址https://www.microchip.com

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SY100E196JITR概述

PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

SY100E196JITR规格参数

参数名称	属性值
零件包装代码	QLCC
包装说明	QCCJ,
针数	28
Reach Compliance Code	compli
Is Samacsys	N
系列	100E
JESD-30 代码	S-PQCC-J28
长度	11.48 mm
逻辑集成电路类型	SILICON DELAY LINE
功能数量	1
抽头/阶步数	127
端子数量	28
输出极性	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY
封装代码	QCCJ
封装形状	SQUARE
封装形式	CHIP CARRIER
可编程延迟线	YES
座面最大高度	4.57 mm
表面贴装	YES
技术	ECL
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
总延迟标称（td）	3.63 ns
宽度	11.48 mm
Base Number Matches	1

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NOT RECOMMENDED FOR NEW DESIGNS

Micrel, Inc.

PROGRAMMABLE DELAY

CHIP WITH ANALOG INPUT

Precision Edge

SY10E196

Precision

SY100E196

Edge

SY10E196

SY100E196

FEATURES

Up to 2ns delay range

Extended 100E V

range of –4.2V to –5.5V

DESCRIPTION

The SY10/100E196 are programmable delay chips

(PDCs) designed primarily for very accurate differential

ECL input edge placement applications.

The delay section consists of a chain of gates and a

linear ramp delay adjustment organized as shown in the

logic diagram. The first two delay elements feature gates

that have been modified to have delays 1.25 and 1.5

times the basic gate delay of approximately 80ps. These

two elements provide the E196 with a digitally-selectable

resolution of approximately 20ps. The required device

delay is selected by the seven address inputs D[0:6],

which are latched on-chip by a high signal on the latch

enable (LEN) control. If the LEN signal is either LOW or

left floating, then the latch is transparent.

The FTUNE input takes an analog coltage and applies

it to an internal linear ramp for reducing the 20s resolution

still further. The FTUNE input is what differentiates the

E196 from the E195.

An eighth latched input, D7, is provided for cascading

multiple PDCs for increased programmable range. The

cascade logic allows full control of multiple PDCs, at the

expense of only a single added line to the data bus for

each additional PDC, without the need for any external

gating.

≈

20ps digital step resolution

Linear input for tighter resolution

>1GHz bandwidth

On-chip cascade circuitry

75Kk

Ω

input pulldown resistor

Fully compatible with Motorola MC10E/100E196

Available in 28-pin PLCC package

PIN NAMES

IN/IN

D[0:7]

Q/Q

LEN

SET MIN

SET MAX

CASCADE

FTUNE

CCO

Function

Signal Input

Input Enable

Mux Select Inputs

Signal Output

Latch Enable

Minimum Delay Set

Maximum Delay Set

Cascade Signal

Linear Voltage Input

to Output

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: H

Amendment: /0

Issue Date: March 2006

SY100E196JITR相似产品对比

	SY100E196JITR	SY100E196	SY10E196	SY10E196_06	SY10E196JC	SY10E196JZTR	SY10E196JCTR	SY10E196JZ	SY100E196JYTR	SY100E196JI
描述	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT
包装说明	QCCJ,	-	-	-	-	LEAD FREE, PLASTIC, LCC-28	QCCJ,	LCC-28	QCCJ,	QCCJ,
Reach Compliance Code	compli	-	-	-	-	compli	compli	compliant	compli	compli
系列	100E	-	-	-	-	10E	10E	10E	100E	100E
JESD-30 代码	S-PQCC-J28	-	-	-	-	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28
长度	11.48 mm	-	-	-	-	11.48 mm	11.48 mm	11.48 mm	11.48 mm	11.48 mm
逻辑集成电路类型	SILICON DELAY LINE	-	-	-	-	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE	SILICON DELAY LINE
功能数量	1	-	-	-	-	1	1	1	1	1
抽头/阶步数	127	-	-	-	-	127	127	127	127	127
端子数量	28	-	-	-	-	28	28	28	28	28
输出极性	COMPLEMENTARY	-	-	-	-	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY	-	-	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	QCCJ	-	-	-	-	QCCJ	QCCJ	QCCJ	QCCJ	QCCJ
封装形状	SQUARE	-	-	-	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	CHIP CARRIER	-	-	-	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
可编程延迟线	YES	-	-	-	-	YES	YES	YES	YES	YES
座面最大高度	4.57 mm	-	-	-	-	4.57 mm	4.57 mm	4.57 mm	4.57 mm	4.57 mm
表面贴装	YES	-	-	-	-	YES	YES	YES	YES	YES
技术	ECL	-	-	-	-	ECL	ECL	ECL	ECL	ECL
端子形式	J BEND	-	-	-	-	J BEND	J BEND	J BEND	J BEND	J BEND
端子节距	1.27 mm	-	-	-	-	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
端子位置	QUAD	-	-	-	-	QUAD	QUAD	QUAD	QUAD	QUAD
总延迟标称（td）	3.63 ns	-	-	-	-	3.63 ns	3.63 ns	3.63 ns	3.63 ns	3.63 ns
宽度	11.48 mm	-	-	-	-	11.48 mm	11.48 mm	11.48 mm	11.48 mm	11.48 mm

SY100E196JITR

SY100E196JITR概述

SY100E196JITR规格参数

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