NOT RECOMMENDED FOR NEW DESIGNS
SY10EL34/L
SY100EL34/L
5V/3.3V
÷2, ÷4, ÷8
Clock Generation Chip
Precision Edge
®
General Description
The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock
generation chips designed explicitly for low-skew clock
generation applications. The internal dividers are
synchronous to each other; therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
BB
output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the V
BB
output should be connected to the
CLK
input and bypassed to ground via a 0.01µF capacitor. The
V
BB
output is designed to act as the switching reference for
the input of the EL34/L under single-ended input
conditions. As a result, this pin can only source/ sink up to
0.5mA of current.
The common enable (
EN
) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal
clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the
falling edge of the divider stages. The internal enable flip-
flop is clocked on the falling edge of the input clock;
therefore, all associated specification limits are referenced
to the negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
Data sheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Precision Edge
®
Features
•
•
•
•
•
•
3.3V and 5V power supply options
50ps output-to-output skew
Synchronous enable/disable
Master Reset for synchronization
Internal 75KΩ input pull-down resistors
Available in 16-pin SOIC package
Pin Description
Pin Name
CLK
EN
Pin Function
Differential clock inputs.
Synchronous enable.
Master reset.
Reference output.
Differential
÷2
outputs.
Differential
÷4
outputs.
Differential
÷8
outputs.
MR
V
BB
Q
0
Q
1
Q
2
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
December 2011
M9999-120611-I
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
Precision Edge
®
SY10EL34/L
SY100EL34/L
Ordering Information
Part Number
SY10EL34LZG
SY10EL34LZGTR
(2)
SY100EL34LZG
SY100EL34LZGTR
(2)
SY10EL34ZG
SY10EL34ZGTR
(2)
SY100EL34ZG
SY100EL34ZGTR
(2)
Notes:
1.
2.
Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
Tape and reel.
Package Type
Z16-2
Z16-2
Z16-2
Z16-2
Z16-2
Z16-2
Z16-2
Z16-2
Operating Range
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Package Marking
SY10EL34LZG with
Pb-Free Bar Line Indicator
SY10EL34LZG with
Pb-Free Bar Line Indicator
SY100EL34LZG with
Pb-Free Bar Line Indicator
SY100EL34LZG with
Pb-Free Bar Line Indicator
SY10EL34ZG with
Pb-Free Bar Line Indicator
SY10EL34ZG with
Pb-Free Bar Line Indicator
SY100EL34ZG with
Pb-Free Bar Line Indicator
SY100EL34ZG with
Pb-Free Bar Line Indicator
Lead Finish
Pb-Free NiPdAu
Pb-Free NiPdAu
Pb-Free NiPdAu
Pb-Free NiPdAu
Pb-Free NiPdAu
Pb-Free NiPdAu
Pb-Free NiPdAu
Pb-Free NiPdAu
Pin Configuration
16-Pin Narrow SOIC (Z16-2)
December 2011
3
M9999-120611-I
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
Precision Edge
®
SY10EL34/L
SY100EL34/L
AC Electrical Characteristics
(1)
(Continued)
V
EE
= V
EE
(minimum) to V
EE
(maximum); V
CC
= GND.
Symbol
T
A
=
+85°C
Propagation Delay to Output
t
PD
t
SKEW
t
S
t
H
V
PP
V
CMR
t
r
t
f
Notes:
1.
Parametric values specified at:
−
5V Power Supply Range:
100EL34 Series:
−4.2V
to
−5.5V
10EL34 Series:
−4.75V
to
−5.5V
3V Power Supply Range:
10/100EL34L Series:
−3.0V
to
−3.8V
Parameter
Min.
Typ.
Max.
Units
CLK
MR
Within-Device Skew
Set-Up Time (
EN
)
Hold Time (
EN
)
Minimum Input Swing
(3)
Common-Mode Range
(4)
Output Rise/Fall Times
Q (20%
−
80%)
960
650
−
400
200
250
−1.4
275
1100
800
−
−
−
−
−
400
1200
1010
50
−
−
−
−0.4
525
ps
ps
ps
ps
mV
V
ps
−
2.
3.
4.
Skew is measured between outputs under identical transitions.
Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the
specified range and the peak-to-peak voltage lies between V
PP
minimum and 1V. The lower end of the CMR range varies 1:1 with V
EE
. The
numbers in the specification table assume a nominal V
EE
=
−3.3V.
Note for PECL operation, the V
CMR(MIN)
will be fixed at 3.3V
−
I
VCMR(MIN)
I.
Truth Table
CLK
Z
ZZ
X
Notes:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
EN
MR
L
L
H
Function
Divide
Hold Q
0
−
2
Reset Q
0
−
2
L
H
X
December 2011
6
M9999-120611-I
hbwhelp@micrel.com
or (408) 955-1690
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