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SY100E452JITR

产品描述5-BIT DIFFERENTIAL REGISTER
产品类别逻辑    逻辑   
文件大小90KB,共4页
制造商Microchip(微芯科技)
官网地址https://www.microchip.com
下载文档 详细参数 全文预览

SY100E452JITR概述

5-BIT DIFFERENTIAL REGISTER

SY100E452JITR规格参数

参数名称属性值
厂商名称Microchip(微芯科技)
零件包装代码QLCC
包装说明QCCJ,
针数28
Reach Compliance Codecompli
其他特性WITH DIFFERENTIAL CLOCK
系列100E
JESD-30 代码S-PQCC-J28
长度11.48 mm
逻辑集成电路类型D FLIP-FLOP
位数5
功能数量1
端子数量28
输出极性COMPLEMENTARY
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装形状SQUARE
封装形式CHIP CARRIER
传播延迟(tpd)0.8 ns
座面最大高度4.57 mm
表面贴装YES
技术ECL
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
触发器类型POSITIVE EDGE
宽度11.48 mm
最小 fmax1100 MHz

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NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc.
5-BIT DIFFERENTIAL
REGISTER
SY10E452
SY100E452
SY10E452
SY100E452
FEATURES
s
s
s
s
s
s
Differential D, CLK and Q
Extended 100E V
EE
range of –4.2V to –5.5V
VBB output for single-ended use
1100MHz min. toggle frequency
Asynchronous Master Reset
Fully compatible with Motorola MC10E/100E452
DESCRIPTION
The SY10/100E452 are 5-bit differential registers with
differential data (inputs and outputs) and clock. The
registers are triggered by a positive transition of the
positive clock (CLK) input. A high on the Master Reset
(MR) asynchronously resets all registers so that the Q
outputs go LOW.
The differential input structures are clamped so that
the inputs of unused registers can be left open without
upsetting the bias network of the devices. The clamping
action will assert the /D and the /CLK sides of the inputs.
Because of the edge-triggered flip-flop nature of the
devices, simultaneously opening both the clock and data
inputs will result in an output which reaches an
unidentified but valid state.
The fully differential design of the devices makes them
ideal for very high frequency applications where a
registered data path is necessary.
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
D
0
D
0
D
Q
R
D
1
D
1
Q
0
Q
0
PIN NAMES
Pin
D [0:4], /D [0:4]
MR
CLK, /CLK
V
BB
Function
Differential Data Inputs
Master Reset Input
Differential Clock Input
V
BB
Reference Output
Differential Data Outputs
V
CC
to Output
D
Q
R
Q
1
Q
1
Q [0:4], Q [0:4]
V
CCO
D
2
D
2
D
Q
R
Q
2
Q
2
D
3
D
3
D
Q
R
Q
3
Q
3
D
4
D
4
CLK
CLK
MR
V
BB
D
Q
R
Q
4
Q
4
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
Rev.: F
Amendment: /0
1
Issue Date: March 2006

 
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