NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc.
5V/3.3V
÷
2,
÷
4/6 CLOCK
GENERATION CHIP
Precision Edge
®
SY10EL38/L
Precision Edge
®
SY100EL38/L
SY10EL38/L
SY100EL38/L
FEATURES
s
s
s
s
s
3.3V and 5V power supply options
50ps output-to-output skew
Synchronous enable/disable
Master Reset for synchronization
Internal 75K
Ω
input pull-down resistors
Precision Edge
®
DESCRIPTION
The SY10/100EL38/L are low skew
÷2, ÷4/6
clock
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
BB
output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the V
BB
output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor.
The V
BB
output is designed to act as the switching
reference for the input of the EL38/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
The Phase_Out output will go HIGH for one clock cycle
whenever the
÷2
and the
÷4/6
outputs are both
transitioning from a LOW to a HIGH. This output allows
for clock synchronization within the system.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL38/Ls in a system.
s
Available in 20-pin SOIC package
Precision Edge is a registered trademark of Micrel, Inc.
M9999-031006
hbwhelp@micrel.com or (408) 955-1690
Rev.: G
Amendment: /0
1
Issue Date: March 2006
Micrel, Inc.
Precision Edge
®
SY10EL38/L
SY100EL38/L
PACKAGE/ORDERING INFORMATION
Ordering Information
(1)
VCC
/EN
DIVSEL
CLK
/CLK
VBB
MR
VCC
PHASED_OUT
/PHASED_OUT
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q0
18 /Q0
17 Q1
16 /Q1
15 Q2
14 /Q2
13 Q3
12 /Q3
11 VEE
Part Number
SY10EL38LZC
SY10EL38LZCTR
(2)
SY100EL38LZC
SY100EL38LZCTR
(2)
SY10EL38LZI
SY10EL38LZITR
(2)
SY100EL38LZI
SY100EL38LZITR
(2)
SY10EL38LZG
(3)
Package
Type
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Package
Marking
SY10EL38LZC
SY10EL38LZC
SY100EL38LZC
SY100EL38LZC
SY10EL38LZI
SY10EL38LZI
SY100EL38LZI
SY100EL38LZI
Lead
Finish
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
SY10EL38LZG with
Pb-Free
Pb-Free bar-line indicator NiPdAu
SY10EL38LZG with
Pb-Free
Pb-Free bar-line indicator NiPdAu
SY100EL38LZG with
Pb-Free
Pb-Free bar-line indicator NiPdAu
SY100EL38LZG with
Pb-Free
Pb-Free bar-line indicator NiPdAu
20-Pin SOIC (Z20-1)
SY10EL38LZGTR
(2, 3)
SY100EL38LZG
(3)
SY100EL38LZGTR
(2, 3)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
M9999-031006
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY10EL38/L
SY100EL38/L
AC ELECTRICAL CHARACTERISTICS
(1)
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= GND
T
A
= -40
°
C
Symbol
f
MAX
t
PD
Parameter
Maximum Toggle Frequency
Propagation Delay to Output
CLK
➝
Output (Diff.)
CLK
➝
Output (S.E.)
MR
➝
Output
Within-Device Skew
(2)
Q
0
— Q
3
All
Part-to-Part
t
S
t
H
V
PP
V
CMR
t
RR
t
PW
t
r
t
f
Set-up Time
Hold Time
Q
0
— Q
3
(Diff.)
All
EN
➝
CLK
DIVSEL
➝
CLK
CLK
➝
EN
CLK
➝
DIVSEL
CLK
Min.
1000
950
900
600
—
—
—
—
300
300
400
400
250
—
CLK
MR
Q
800
700
280
—
—
—
—
—
—
—
—
150
—
150
200
—
—
—
—
—
—
—
1150
1200
900
50
75
200
240
—
—
—
—
—
–0.4
100
—
—
550
T
A
= 0
°
C
1000
950
900
600
—
—
—
—
—
—
400
400
250
–1.4
—
800
700
280
—
—
—
—
—
—
—
—
150
—
150
200
—
—
—
—
—
—
—
1150
1200
900
50
75
200
240
—
—
—
—
—
–0.4
100
—
—
550
T
A
= +25
°
C
1000
970
920
600
—
—
—
—
—
—
400
400
250
–1.4
—
800
700
280
—
—
—
—
—
—
—
—
150
—
150
200
—
—
—
—
—
—
—
T
A
= +85
°
C
Min.
1000
Typ. Max. Unit
—
—
—
—
—
—
—
—
150
—
150
200
—
—
—
—
—
—
—
1250
1300
900
50
75
200
240
—
—
—
—
—
–0.4
100
—
—
550
ps
ps
mV
V
ps
ps
ps
ps
MHz
ps
1170 1050
1220 1000
900 600
50
75
200
240
—
—
—
—
—
–0.4
100
—
—
550
—
—
—
—
—
—
400
400
250
–1.4
—
800
700
280
Typ. Max. Min. Typ. Max. Min. Typ. Max.
t
skew
Minimum Input Swing
(3)
Common Mode Range
(4)
Reset Recovery Time
Minimum Pulse Width
Output Rise/Fall Times
(20% —80%)
CLK –1.3
NOTES:
1. Parametric values specified at:
5 volt Power Supply Range
3 volt Power Supply Range
2. Skew is measured between outputs under identical transitions.
3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between V
PP
min. and 1V. The lower end of the CMR range varies 1:1 with V
EE
. The numbers in the spec table
assume a nominal V
EE
= –3.3V. Note for PECL operation, the V
CMR
(min) will be fixed at 3.3V – IV
CMR
(min)I.
100EL38 Series:
10EL38 Series
10/100EL38L Series:
-4.2V to -5.5V.
-4.75V to -5.5V.
-3.0V to -3.8V.
M9999-031006
hbwhelp@micrel.com or (408) 955-1690
4
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
