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SY100EL52ZC: 产品描述DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP; 产品类别逻辑逻辑; 文件大小49KB，共4页; 制造商Microchip(微芯科技); 官网地址https://www.microchip.com

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SY100EL52ZC概述

DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP

SY100EL52ZC规格参数

参数名称	属性值
厂商名称	Microchip(微芯科技)
包装说明	SOP,
Reach Compliance Code	compli
其他特性	WITH DIFFERENTIAL CLOCK
系列	100EL
JESD-30 代码	R-PDSO-G8
长度	4.93 mm
逻辑集成电路类型	D FLIP-FLOP
位数	1
功能数量	1
端子数量	8
输出极性	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
传播延迟（tpd）	0.465 ns
座面最大高度	1.73 mm
表面贴装	YES
技术	ECL
端子形式	GULL WING
端子节距	1.27 mm
端子位置	DUAL
触发器类型	POSITIVE EDGE
宽度	3.94 mm
最小 fmax	2200 MHz

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DIFFERENTIAL DATA AND

CLOCK D FLIP-FLOP

SY10EL52

SY100EL52

FEATURES

365ps propagation delay

2.0GHz toggle frequency

Internal 75K

Ω

input pull-down resistors

Available in 8-pin SOIC package

DESCRIPTION

The SY10/100EL52 are differential data, differential

clock D flip-flops. These devices are functionally

equivalent to the E452 devices, with higher performance

capabilities. With propagation delays and output transition

times significantly faster than the E452, the EL52 is ideally

suited for those applications which require the ultimate

in AC performance.

Data enters the master portion of the flip-flop when

the clock is LOW and is transferred to the slave, and

thus the outputs, upon a positive transition of the clock.

The differential clock inputs also allow the EL52 to be

used as a negative edge triggered device.

The EL52 employs input clamping circuitry so that,

under open input conditions (pulled down to V

), the

outputs of the device will remain stable.

PIN CONFIGURATION/BLOCK DIAGRAM

CLK

Flip-Flop

SOIC

TOP VIEW

PIN NAMES

CLK

Data Input

Clock Input

Data Output

Function

TRUTH TABLE

(1)

NOTE:

1. Z = LOW-to-HIGH transition.

CLK

Rev.: F

Amendment: /0

Issue Date: August, 1998

SY100EL52ZC相似产品对比

	SY100EL52ZC	SY10EL52ZC	SY10EL52ZCTR	SY10EL52	SY100EL52ZCTR
描述	DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP	DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP	DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP	DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP	DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP
厂商名称	Microchip(微芯科技)	Microchip(微芯科技)	Microchip(微芯科技)	-	Microchip(微芯科技)
包装说明	SOP,	SOP,	SOP,	-	SOP,
Reach Compliance Code	compli	compli	compli	-	compli
其他特性	WITH DIFFERENTIAL CLOCK	WITH DIFFERENTIAL CLOCK	WITH DIFFERENTIAL CLOCK	-	WITH DIFFERENTIAL CLOCK
系列	100EL	10EL	10EL	-	100EL
JESD-30 代码	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	-	R-PDSO-G8
长度	4.93 mm	4.93 mm	4.93 mm	-	4.93 mm
逻辑集成电路类型	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	-	D FLIP-FLOP
位数	1	1	1	-	1
功能数量	1	1	1	-	1
端子数量	8	8	8	-	8
输出极性	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	-	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
封装代码	SOP	SOP	SOP	-	SOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
封装形式	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	-	SMALL OUTLINE
传播延迟（tpd）	0.465 ns	0.465 ns	0.465 ns	-	0.465 ns
座面最大高度	1.73 mm	1.73 mm	1.73 mm	-	1.73 mm
表面贴装	YES	YES	YES	-	YES
技术	ECL	ECL	ECL	-	ECL
端子形式	GULL WING	GULL WING	GULL WING	-	GULL WING
端子节距	1.27 mm	1.27 mm	1.27 mm	-	1.27 mm
端子位置	DUAL	DUAL	DUAL	-	DUAL
触发器类型	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	-	POSITIVE EDGE
宽度	3.94 mm	3.94 mm	3.94 mm	-	3.94 mm
最小 fmax	2200 MHz	2200 MHz	2200 MHz	-	2200 MHz

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