CBTU0808
Dual lane PCI Express port multiplexer
Rev. 02 — 6 September 2007
Product data sheet
1. General description
The CBTU0808 is a dual lane port multiplexer designed to provide convenient and reliable
path switching for PCI Express signals. It is organized as two PCI Express lanes, each
consisting of a Transmit and Receive channel. Each channel has four ports, two (A and B)
on the source (or host) side and two (A and B) on the destination (or device) side. Each
port provides a pair of signal lines to support PCIe differential signaling.
Using specially designed high-bandwidth and high off-isolation switch elements, source
and destination ports can be connected or isolated in three possible configurations:
source A and B to destinations A and B respectively; or source A to destination B
(remaining ports isolated), or all ports isolated.
The switch elements are controlled by internal control logic to set switch positions in
accordance with these three configurations, selectable by CMOS inputs CTRL0 and
CTRL1 for lanes 0 and 1 respectively. Within a lane, the switch configuration is always
applied identically to both transmit and receive channels.
The CBTU0808 is packaged in a 48-ball, depopulated 9
×
9 grid, 0.5 mm ball pitch, thin
profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum
5 mm
×
5 mm of board space) allows for adequate signal routing and escape using
conventional board technology.
2. Features
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2-lane wide PCI Express port multiplexer
One transmit and one receive differential channel per lane
Four ports per channel
PCI Express signaling compliant
High bandwidth: > 1 GHz
Low OFF-feedthrough of <
−35
dB at 1.25 GHz
Low channel crosstalk of <
−35
dB at 1.25 GHz
Designed to match characteristic impedance of PCIe signaling environment
Single 1.8 V supply operation
ESD resilience of 8 kV HBM
Available in 48-ball, 5 mm
×
5 mm, 0.5 mm ball pitch TFBGA package, Pb-free/Green
3. Applications
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High-performance computing applications
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Port switching and docking applications
NXP Semiconductors
CBTU0808
Dual lane PCI Express port multiplexer
4. Ordering information
Table 1.
Ordering information
Solder process
Package
Name
CBTU0808EE/G Pb-free (SnAgCu solder ball
compound)
TFBGA48
Description
plastic thin fine-pitch ball grid array package;
48 balls; body 5
×
5
×
0.8 mm
Version
SOT918-1
Type number
5. Functional diagram
CBTU0808
CTRL[1:0]
TEST[1:0]
TXSA0P
TXSA0N
channel Tx0
TXSB0P
TXSB0N
LANE 0
RXSA0P
RXSA0N
channel Rx0
RXSB0P
RXSB0N
RXDB0P
RXDB0N
RXDA0P
RXDA0N
TXDB0P
TXDB0N
CONTROL AND CONFIGURATION
TXDA0P
TXDA0N
TXSA1P
TXSA1N
channel Tx1
TXSB1P
TXSB1N
LANE 1
RXSA1P
RXSA1N
channel Rx1
RXSB1P
RXSB1N
TXDA1P
TXDA1N
TXDB1P
TXDB1N
RXDA1P
RXDA1N
RXDB1P
RXDB1N
002aac139
Fig 1. Functional diagram
CBTU0808_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 6 September 2007
2 of 17
NXP Semiconductors
CBTU0808
Dual lane PCI Express port multiplexer
6. Pinning information
6.1 Pinning
ball A1
index area
CBTU0808EE/G
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
002aac213
Transparent top view
Fig 2. Pin configuration for TFBGA48
1
A
B
C
D
E
F
G
H
J
TXSB1P
TEST0
RXSB0P
GND
TXSA1P
CTRL0
RXSA0P
2
TXSB0P
GND
RXSA0N
RXSB0N
V
DD
TXSA1N
TXSB1N
GND
RXSA1P
3
4
TXSA0P
5
GND
V
DD
6
TXDA0P
TXDA0N
7
8
TXDB0P
9
TEST1
RXDA0P
TXSB0N
TXSA0N
TXDB0N
GND
RXDA0N
RXDB0N
V
DD
TXDA1N
TXDB1N
RXDB0P
GND
TXDA1P
RXSA1N
RXSB1N
RXSB1P
V
DD
GND
RXDB1N
RXDB1P
RXDA1N
GND
RXDA1P
TXDB1P
CTRL1
002aac212
48-ball, 9
×
9 grid; top view. An empty cell indicates no ball is populated at that grid point.
Fig 3. Ball mapping
CBTU0808_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 6 September 2007
3 of 17
NXP Semiconductors
CBTU0808
Dual lane PCI Express port multiplexer
6.2 Pin description
Table 2.
Test and
control
Pin description
Symbol
CTRL0
CTRL1
TEST0
Pin
A1
J9
J1
Type
CMOS
input
CMOS
input
Description
Switch configuration control inputs. See
Table 3 “Switch configuration truth table”.
Test input. Used for test purposes only.
Should be left open-circuit during normal
operation. An internal pull-down resistor
will default this pin to a LOW state.
Test output. Used for test purposes only.
Should be left open-circuit in normal
application.
Transmit ports A and B differential signal
terminals for Lane 0, Source side.
Receive ports A and B differential signal
terminals for Lane 0, Source side.
Transmit ports A and B differential signal
terminals for Lane 1, Source side.
Receive ports A and B differential signal
terminals for Lane 1, Source side.
Transmit ports A and B differential signal
terminals for Lane 0, Destination side.
Receive ports A and B differential signal
terminals for Lane 0, Destination side.
Transmit ports A and B differential signal
terminals for Lane 1, Destination side.
Receive ports A and B differential signal
terminals for Lane 1, Destination side.
power supply pins
ground pins
Signal group
TEST1
A9
output
Signal ports
TXSA0P, TXSA0N,
TXSB0P, TXSB0N
A4, B4,
A2, B3
signal
port
signal
port
signal
port
signal
port
signal
port
signal
port
signal
port
signal
port
power
power
RXSA0P, RXSA0N, B1, C2,
RXSB0P, RXSB0N D1, D2
TXSA1P, TXSA1N,
TXSB1P, TXSB1N
F1, F2,
H1, G2
RXSA1P, RXSA1N, J2, H3,
RXSB1P, RXSB1N J4, H4
TXDA0P, TXDA0N,
TXDB0P, TXDB0N
A6, B6,
A8, B7
RXDA0P, RXDA0N, B9, C8,
RXDB0P, RXDB0N D9, D8
TXDA1P, TXDA1N,
TXDB1P, TXDB1N
F9, F8,
H9, G8
RXDA1P, RXDA1N, J8, H7,
RXDB1P, RXDB1N J6, H6
Power
V
DD
GND
B5, E2,
E8, H5
A5, B2,
B8, E1,
E9, H2,
H8, J5
CBTU0808_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 6 September 2007
4 of 17
NXP Semiconductors
CBTU0808
Dual lane PCI Express port multiplexer
7. Functional description
7.1 Functional description
7.1.1 General information
The CBTU0808 Dual lane PCI Express port multiplexer is designed to allow port switching
of up to two PCI Express lanes (each including a Transmit and Receive channel)
according to three switch configuration settings (described in
Section 7.1.2.1).
The basic
switch element of the CBTU0808 is designed integrally with its package and chip
interconnect to present an optimum characteristic on-impedance when used in a
PCI Express signaling environment, and to provide high off-port isolation and low
crosstalk.
7.1.2 Functional information
The following paragraphs describe the control and configuration possibilities available in
the CBTU0808.
7.1.2.1
Switch configuration
The position of the port switches is controlled by CMOS input signals CTRL[1:0] and can
be overridden by CMOS input TEST0 to disconnect (open) all ports between source and
destination. For a given lane, the switch positions are always identical between transmit
and receive channels. Lane 0 is controlled by CTRL0 and Lane 1 is controlled by CTRL1.
The truth table for the switch position as a function of these inputs is shown in
Table 3.
Table 3.
Inputs
CTRLn
[1]
TEST0
LOW
HIGH
[2]
LOW
> LOW
[1]
[2]
Switch configuration truth table
Function
Source ports
[1]
An
Bn
LOW
HIGH
HIGH
An
Bn
An
Bn
Destination ports
A
LOW
R
on
high-Z
high-Z
high-Z
high-Z
high-Z
B
high-Z
R
on
R
on
high-Z
high-Z
high-Z
SA:DA/SB:DB
(Dual Through mode)
SA:DB
(Single Cross mode)
All ports open-circuit
(Disconnect mode)
do not use
Comment
Test mode for internal use only
n is the Lane number (0 or 1).
CTRL1 or CTRL0 = HIGH.
CBTU0808_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 6 September 2007
5 of 17
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