512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
DDR2 SDRAM Registered DIMM (RDIMM)
MT18HTF6472 – 512MB
MT18HTF12872(P) – 1GB
MT18HTF25672(P) – 2GB
For component data sheets, refer to Micron's Web site:
www.micron.com
Features
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, PC2-
5300, or PC2-6400
• Supports ECC error detection and correction
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Single rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1:
240-Pin RDIMM (MO-237
R/C C–Non-Parity, R/C H–Parity)
PCB height: 30mm (1.18in)
Options
• Parity
3
• Operating temperature
1
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
240-pin DIMM (Pb-free)
• Frequency/CAS latency
2
–
2.5ns @CL = 5 (DDR2-800)
3
–
2.5ns @ CL = 6 (DDR2-800)
3
–
3.0ns @ CL = 5 (DDR2-667)
3
–
3.75ns @ CL = 4 (DDR2-533)
–
5.0ns @ CL = 3 (DDR2-400)
• PCB height
–
30mm (1.18in)
Marking
P
None
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
3. Not available in 512MB density.
Table 1:
Speed
Grade
-80E
Key Timing Parameters
Industry
Nomenclature
PC2-6400
Data Rate (MT/s)
CL = 6
–
CL = 5
800
CL = 4
533
533
533
533
400
CL = 3
–
t
RCD
(ns)
12.5
RP
(ns)
12.5
t
RC
(ns)
55
t
-800
-667
-53E
-40E
PC2-6400
PC2-5300
PC2-4200
PC2-3200
800
–
–
–
667
667
–
–
–
400
400
400
15
15
15
15
15
15
15
15
55
55
55
55
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
Table 2:
Addressing
512MB
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
8K
8K (A0–A12)
4 (BA0, BA1)
1KB
256Mb (64 Meg x 4)
2K (A0–A9, A11)
1 (S0#)
1GB
8K
16K (A0–A13)
4 (BA0, BA1)
1KB
512Mb (128 Meg x 4)
2K (A0–A9, A11)
1 (S0#)
2GB
8K
16K (A0–A13)
8 (BA0, BA1, BA2)
1KB
1Gb (256 Meg x 4)
2K (A0–A9, A11)
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M4,
1
256Mb DDR2 SDRAM
Module
Density
512MB
512MB
Configuration
64 Meg x 72
64 Meg x 72
Module
Bandwidth
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
4-4-4
3-3-3
Part Number
2
MT18HTF6472Y-53E__
MT18HTF6472Y-40E__
Table 4:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H128M4,
1
512Mb DDR2 SDRAM
Module
Density
1GB
1GB
1GB
1GB
1GB
Configuration
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
2
MT18HTF12872(P)Y-80E__
MT18HTF12872(P)Y-800__
MT18HTF12872(P)Y-667__
MT18HTF12872(P)Y-53E__
MT18HTF12872(P)Y-40E__
Table 5:
Part Numbers and Timing Paramters – 2GB Modules
Base device: MT47H256M4,
1
1Gb DDR2 SDRAM
Module
Density
2GB
2GB
2GB
2GB
2GB
Configuration
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
Module
Bandwith
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
2
MT18HTF25672(P)Y-80E__
MT18HTF25672(P)Y-800__
MT18HTF25672(P)Y-667__
MT18HTF25672(P)Y-53E__
MT18HTF25672(P)Y-40E__
Notes:
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT18HTF6472Y-667D2.
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 6:
Pin Assignments
240-Pin RDIMM Front
Pin Symbol Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
240-Pin RDIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
Vss
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
1
55
2
56
57
58
59
60
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
V
DD
Q
CKE0
V
DD
NC/BA2
NC/
E
RR
_O
UT
V
DD
Q
A11
A7
V
DD
A5
61
62
63
64
65
66
67
68
3
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A4
V
DD
Q
A2
V
DD
V
SS
V
SS
V
DD
NC/
P
AR
_I
N
V
DD
A10
BA0
V
DDQ
WE#
CAS#
V
DD
Q
S1#
ODT1
V
DD
Q
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DQS9
DQS9#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DQS10
DQS10#
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DQS11
DQS11#
V
SS
DQ22
DQ23
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
V
SS
DQ28
DQ29
V
SS
DQS12
DQS12#
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DQS17
DQS17#
V
SS
CB6
CB7
V
SS
V
DD
Q
CKE1
V
DD
NC
NC
V
DD
Q
A12
A9
V
DD
A8
A6
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
4
197
198
199
200
201
202
203
204
205
206
207
208
209
210
V
DDQ
A3
A1
V
DD
CK0
CK0#
V
DD
A0
V
DD
BA1
V
DD
Q
RAS#
S0#
V
DD
Q
ODT0
NC/A13
V
DD
V
SS
DQ36
DQ37
V
SS
DQS13
DQS13#
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
DQS14
DQS14#
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
SS
DQS15
DQS15#
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS16
DQS16#
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
Notes:
1.
2.
3.
4.
Pin 54 is NC for 512MB and 1GB or BA2 for 2GB.
Pin 55 is NC for non-parity and E
RR
_O
UT
for parity.
Pin 68 is NC for non-parity and P
AR
_I
N
for parity.
Pin 196 is NC for 512MB or A13 for 1GB and 2GB.
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments and Descriptions
Table 7:
Symbol
ODT0
Pin Descriptions
Type
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Description
On-die termination:
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#,
and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Bank address inputs:
BA0–BA1/BA2 define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE
command.
Address inputs:
Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Parity bit for the address and control bus.
CK0, CK0#
CKE0
S0#
RAS#, CAS#,
WE#
BA0, BA1
(512MB, 1GB)
BA0, BA1, BA2
(2GB)
A0–A12
(512MB)
A0–A13
(1GB, 2GB)
Input
(SSTL_18)
P
AR
_I
N
SCL
Serial clock for presence-detect:
SCL is used to synchronize the presence-detect data
transfer to and from the module.
SA0–SA2
Input
Presence-detect address inputs:
These pins are used to configure the presence-detect
device.
RESET#
Input
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be
(LVCMOS) used during power-up to ensure that CKE is LOW and DQs are High-Z.
DQS0–DQS17,
I/O
Data strobe:
Output with read data, input with write data for source synchronous
DQS0#–DQS17# (SSTL_18) operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
DQ0–DQ63
I/O
Data input/output:
Bidirectional data bus.
(SSTL_18)
CB0–CB7
I/O
Check bits.
(SSTL_18)
SDA
I/O
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module.
Output
E
RR
_O
UT
Parity error found on the address and control bus.
(open drain)
Supply
V
DD
/V
DD
Q
Power supply:
1.8V ±0.1V.
Supply
V
REF
SSTL_18 reference voltage.
V
SS
Supply
Ground.
Supply
V
DDSPD
Serial EEPROM positive power supply:
+1.7V to +3.6V.
NC
–
No connect:
These pins should be left unconnected.
DNU
–
Do not use.
Input
(SSTL_18)
Input
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
V
SS
RS0#
DQS0
DQS0#
DM
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
DM
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2#
DM
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3#
DM
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4#
DM
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5#
DM
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6#
DM
DQ48
DQ49
DQ50
DQ51
DQS7
DQS7#
DM
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8#
DM
CB0
CB1
CB2
CB3
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQS9
DQS9#
DM
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10#
DM
DQ12
DQ13
DQ14
DQ15
DQS11
DQS11#
DM
DQ20
DQ21
DQ22
DQ23
DQS12
DQS12#
DM
DQ28
DQ29
DQ30
DQ31
DQS13
DQS13#
DM
DQ36
DQ37
DQ38
DQ39
DQS14
DQS14#
DM
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15#
DM
DQ52
DQ53
DQ54
DQ55
DQS16
DQS16#
DM
DQ60
DQ61
DQ62
DQ63
DQS17
DQS17#
DM
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
CS# DQS DQS#
U1
U22
U2
U21
U3
U20
U4
U19
U9
U16
U10
U15
U11
U14
U12
U13
U5
U18
U6, U17
P
AR
_I
N
S0#
BA0–BA1/BA2
A0–A12/A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
R
e
g
i
s
t
e
r
E
RR
_O
UT
RS0#: DDR2 SDRAM
RBA0–RBA1/RBA2: DDR2 SDRAM
RA0–RA12/RA13: DDR2 SDRAM
RRAS#: DDR2 SDRAM
RCAS#: DDR2 SDRAM
V
DDSPD
RWE#: DDR2 SDRAM
RCKE0: DDR2 SDRAM
V
DD
/V
DD
Q
RODT0: DDR2 SDRAM
U8
CK0
CK0#
RESET#
PLL
SPD EEPROM
U7
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
SCL
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
Register x 2
SPD EEPROM
WP A0
A1
A2
V
SS
SA0 SA1 SA2
SDA
V
REF
V
SS
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
