512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM Unbuffered DIMM
MT16HTF6464A – 512MB
MT16HTF12864A – 1GB
MT16HTF25664A – 2GB
For component specifications, refer to the Micron’s Web site:
www.micron.com/ddr2
Features
• 240-pin, unbuffered, dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, PC2-
5300, or PC2-6400
• 512MB (64 Meg x 64), 1GB (128 Meg x 64), and 2GB
(256 Meg x 64)
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Dual rank
Figure 1:
240-Pin DIMM (MO-237 R/C “B”)
PCB height: 29.97mm (1.18in)
Options
• Package
240-pin DIMM (lead-free)
• Frequency/CL
1
2.5ns @ CL = 5 (DDR2-800)
2
3.0ns @ CL = 5 (DDR2-667)
3
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
29.97mm (1.18in)
Notes: 1. CL = CAS (READ) latency.
2. Not available in 512MB density.
3. Not available in 2GB density.
Marking
Y
-80E
-667
-53E
-40E
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Features
Table 1:
Address Table
512MB
Refresh count
Row addressing
Device bank addressing
Device page size per bank
Device configuration
Column addressing
Module rank addressing
8K
8K (A0–A12)
4 (BA0, BA1)
1KB
256Mb (32 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
1GB
8K
16K (A0–A13)
4 (BA0, BA1)
1KB
512Mb (64 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
2GB
8K
16K (A0–A13)
8 (BA0, BA1, BA2)
1KB
1Gb (128 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
Table 2:
Key Timing Parameters
Data Rate (MT/s)
t
Speed Grade
-80E
-667
-53E
-40E
CL = 3
–
400
400
400
CL = 4
533
533
533
400
CL = 5
800
667
–
–
RCD
(ns)
12.5
15
15
15
RP
(ns)
12.5
15
15
15
t
RC
(ns)
55
55
55
55
t
Table 3:
Part Numbers and Timing Parameters
Module
Density
512MB
512MB
512MB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
Configuration
64 Meg x 64
64 Meg x 64
64 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
4-4-4
3-3-3
5-5-5
5-5-5
4-4-4
3-3-3
5-5-5
5-5-5
4-4-4
3-3-3
Part Number
1
MT16HTF6464AY-667__
MT16HTF6464AY-53E__
MT16HTF6464AY-40E__
MT16HTF12864AY-80E__
MT16HTF12864AY-667__
MT16HTF12864AY-53E__
MT16HTF12864AY-40E__
MT16HTF25664AY-80E__
MT16HTF25664AY-667__
MT16HTF25664AY-53E__
MT16HTF25664AY-40E__
Notes:
1. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT16HTF12864AY-80ED4.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignment
240-pin DIMM Front
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
DDQ
CKE0
V
DD
NC/BA2
NC
V
DDQ
A11
A7
V
DD
A5
Note:
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Symbol
A4
V
DDQ
A2
V
DD
V
SS
V
SS
V
DD
NC
V
DD
A10/AP
BA0
V
DDQ
WE#
CAS#
V
DDQ
S1#
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
CK1#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
240-pin DIMM Back
Symbol
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
NC
V
SS
DM8
NC
V
SS
NC
NC
V
SS
V
DDQ
CKE1
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Symbol
V
DDQ
A3
A1
V
DD
CK0
CK0#
V
DD
A0
V
DD
BA1
V
DDQ
RAS#
S0#
V
DDQ
ODT0
NC/A13
V
DD
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK2
CK2#
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
Pin 196 is NC for 512MB, or A13 for 1GB and 2GB; pin 54 is NC for 512MB and 1GB, or BA2
for 2GB.
Figure 2:
Front View
U1
U2
Pin Locations
Back View
U3
U4
U19
U6
U7
U8
U9
U10
U11
U12
U13
U15
U16
U17
U18
PIN 1
PIN 64
PIN 65
PIN 120
PIN 240
PIN 185
PIN 184
PIN 121
Indicates a V
DD
or V
DD
Q pin
Indicates a V
SS
pin
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
77, 195
Symbol
ODT0, ODT1
Type
Input
Description
On-die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE
(registered LOW) deactivates clocking circuitry on the DDR2
SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides precharge power-down and SELF
REFRESH operations (all device banks idle), or ACTIVE power-
down (row ACTIVE in any device bank). CKE is synchronous for
power-down entry, power-down exit, output disable, and for
SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit.
Input buffers (excluding CK, CK#, CKE, and ODT) are disabled
during power-down. Input buffers (excluding CKE) are disabled
during SELF REFRESH. CKE is an SSTL_18 input but will detect a
LVCMOS LOW level when V
DD
is applied during first power-up.
After V
REF
has become stable during the power on and
initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper SELF REFRESH
operation, V
REF
must be maintained to this input.
Chip select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when
S# is registered HIGH. S# provides for external rank selection on
systems with multiple ranks. S# is considered part of the
command code.
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1/BA2 define which mode register including
MR, EMR, EMR(2), and EMR(3) is loaded during the LMR
command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the precharge applies to one
device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LMR command.
Input data mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
137, 138, 185, 186, 220, 221
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
CKE0, CKE1
Input
52, 171
Input
76, 193
S0#, S1#
Input
73, 74, 192
54
(2GB),
71, 190
RAS#, CAS#, WE#
BA0, BA1,
BA2
(2GB)
Input
Input
57, 58, 60, 61, 63, 70, 176, A0–A12
(512MB)
177, 179, 180, 182, 183, 188, A0–A13
(1GB, 2GB)
196
(1GB, 2GB)
Input
125, 134, 146, 155, 202, 211,
223, 232
DM0–DM7
Input
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
120
101, 239, 240
3, 4, 9, 10, 12, 13, 21, 22, 24,
25, 30, 31, 33, 34, 39, 40, 80,
81, 86, 87, 89, 90, 95, 96, 98,
99, 107, 108, 110, 111, 116,
117, 122, 123, 128, 129, 131,
132, 140, 141, 143, 144, 149,
150, 152, 153, 158, 159, 199,
200, 205, 206, 208, 209, 214,
215, 217, 218, 226, 227, 229,
230, 235, 236
6, 7, 15, 16, 27, 28, 36, 37,
83, 84, 92, 93, 104, 105, 113,
114,
Symbol
SCL
SA0–SA2
DQ0–DQ63
Type
Input
Input
I/O
Description
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-detect address inputs: These pins are used to configure
the presence-detect device.
Data Input/output: Bidirectional data bus.
DQS0–DQS7,
DQS0#–DQS7#
119
SDA
53, 59, 64, 67, 69, 172, 178,
184, 187, 189, 197,
51, 56, 62, 72, 75, 78, 170,
175, 181, 191, 194,
1
2, 5, 8, 11, 14, 17, 20, 23, 26,
29, 32, 35, 38, 41, 44, 47, 50,
65, 66, 79, 82, 85, 88, 91, 94,
97,100, 103, 106, 109,112,
115, 118, 121, 124, 127, 130,
133, 136, 139, 142, 145, 148,
151, 154, 157, 160, 163, 166,
169, 198, 201, 204, 207, 210,
213, 216, 219, 222, 225, 228,
231, 234, 237
238
18, 19, 42, 43, 45, 46, 48, 49,
54 (512MB, 1GB), 55, 68, 76,
102, 125, 126, 134, 135, 146,
147, 155, 156, 161, 162, 164,
165, 167, 168, 171, 173, 174,
196 (512MB), 202, 203, 211,
212, 223, 224, 232, 233
V
DD
V
DD
Q
V
REF
V
SS
Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
I/O
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
Supply Power supply: +1.8V ±0.1V.
Supply DQ Power supply: +1.8V ±0.1V.
Supply SSTL_18 reference voltage.
Supply Ground.
I/O
V
DDSPD
NC
Supply Serial EEPROM positive power supply: +1.7V to +3.6V.
–
No connect: These pins should be left unconnected.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
