256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT8HTF3264AY – 256MB
MT8HTF6464AY – 512MB
MT8HTF12864AY – 1GB
Features
•
240-pin, unbuffered dual in-line memory module
•
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, PC2-6400, or PC2-8500
•
256MB (32 Meg x 64), 512MB (64 Meg x 64),
or 1GB (128 Meg x 64
•
V
DD
= V
DDQ
= 1.8V
•
V
DDSPD
= 1.7–3.6V
•
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
•
Differential data strobe (DQS, DQS#) option
•
4n-bit prefetch architecture
•
Multiple internal device banks for concurrent
operation
•
Programmable CAS latency (CL)
•
Posted CAS additive latency (AL)
•
WRITE latency = READ latency - 1
t
CK
•
Programmable burst lengths (BL): 4 or 8
•
Adjustable data-output drive strength
•
64ms, 8192-cycle refresh
•
On-die termination (ODT)
•
Serial presence detect (SPD) with EEPROM
•
Gold edge contacts
•
Single rank
Table 1: Key Timing Parameters
Speed
Grade
-1GA
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-8500
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 7
1066
CL = 6
800
800
800
–
–
–
CL = 5
667
800
667
667
–
–
CL = 4
533
533
533
553
553
400
CL = 3
400
400
400
400
400
400
t
RCD
t
RP
t
RC
Figure 1: 240-Pin UDIMM (MO-237 R/C A and D)
PCB height: 30.0mm (1.18in)
Options
•
Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
1
•
Package
–
240-pin DIMM (lead-free)
•
Frequency/CL
2
–
1.875ns @ CL = 7 (DDR2-1066)
3
–
2.5ns @ CL = 5 (DDR2-800)
–
2.5ns @ CL = 6 (DDR2-800)
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
4
–
5.0ns @ CL = 3 (DDR2-400)
Notes:
Marking
None
I
Y
-1GA
-80E
-800
-667
-53E
-40E
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Available only in 1GB, Rev. E devices.
4. Not recommended for new designs.
(ns)
13.125
12.5
15
15
15
15
(ns)
13.125
12.5
15
15
15
15
(ns)
58.125
57.5
60
60
55
55
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
256MB
8K
16K A[12:0]
4 BA[2:0]
256Mb (32 Meg x 8)
1K A[9:0]
1 S0#
512MB
8K
16K A[13:0]
4 BA[2:0]
512Mb (64 Meg x 8)
1K A[9:0]
1 S0#
1GB
8K
16K A[13:0]
8 BA[3:0]
1Gb (128 Meg x 8)
1K A[9:0]
1 S0#
Table 3: Part Numbers and Timing Parameters – 256MB Modules (End of Life)
Base device: MT47H32M8,
1
256Mb DDR2 SDRAM
Module
2
Part Number
Density
Configuration
MT8HTF3264A(I)Y-667__
MT8HTF3264A(I)Y-53E__
MT8HTF3264A(I)Y-40E__
256MB
256MB
256MB
32 Meg x 64
32 Meg x 64
32 Meg x 64
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
5-5-5
4-4-4
3-3-3
Table 4: Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M8,
1
512Mb DDR2 SDRAM
Module
2
Part Number
Density
Configuration
MT8HTF6464A(I)Y-80E__
MT8HTF6464A(I)Y-800__
MT8HTF6464A(I)Y-667__
MT8HTF6464A(I)Y-53E__
MT8HTF6464A(I)Y-40E__
512MB
512MB
512MB
512MB
512MB
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
Module
Bandwidth
6.2 GB/s
6.2 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
Table 5: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H128M8,
1
1Gb DDR2 SDRAM
Module
2
Part Number
Density
Configuration
MT8HTF12864A(I)Y-1GA__
MT8HTF12864A(I)Y-80E__
MT8HTF12864A(I)Y-800__
MT8HTF12864A(I)Y-667__
MT8HTF12864A(I)Y-53E__
MT8HTF12864A(I)Y-40E__
Notes:
1GB
1GB
1GB
1GB
1GB
1GB
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
Module
Bandwidth
8.5 GB/s
6.2 GB/s
6.2 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
1.875ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
7-7-7
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT8HTF12864AY-667E1.
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments
Pin Assignments
Table 6: Pin Assignments
240-Pin UDIMM Front
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
DDQ
CKE0
V
DD
NC/BA2
1
NC
V
DDQ
A11
A7
V
DD
A5
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Symbol
A4
V
DDQ
A2
V
DD
V
SS
V
SS
V
DD
NC
V
DD
A10
BA0
V
DDQ
WE#
CAS#
V
DDQ
NC
NC
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
CK1#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
240-Pin UDIMM Back
Symbol
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
DDQ
NC
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Symbol
V
DDQ
A3
A1
V
DD
CK0
CK0#
V
DD
A0
V
DD
BA1
V
DDQ
RAS#
S0#
V
DDQ
ODT0
NC/A13
2
V
DD
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK2
CK2#
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
Notes:
1. Pin 54 is NC for 256MB and 512MB or BA2 for 1GB.
2. Pin 196 is NC for 256MB or A13 for 512MB and 1GB.
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Ax
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs:
Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
Clock:
Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
Data mask (x8 devices only):
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination:
Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
Used to configure the SPD EEPROM address range on the I
2
C
bus.
Serial clock for SPD EEPROM:
Used to synchronize communication to and from the
SPD EEPROM on the I
2
C bus.
Check bits.
Used for system error detection and correction.
Data input/output:
Bidirectional data bus.
Data strobe:
Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
BAx
Input
CKx,
CK#x
CKEx
DMx,
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
S#x
SAx
SCL
CBx
DQx
DQSx,
DQS#x
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2003 Micron Technology, Inc. All rights reserved.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
