128MB, 256MB, 512MB (x64, SR)
184-PIN DDR SDRAM UDIMM
DDR SDRAM
UNBUFFERED DIMM
Features
• 184-pin dual in-line memory module (DIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 128MB (16 Meg x 64), 256MB (32 Meg x 64), and
512MB (64 Meg x 64)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs (128MB), 7.8125µs (256MB, 512MB)
maximum average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
MT8VDDT1664A – 128MB
MT8VDDT3264A – 256MB
MT8VDDT6464A – 512MB
Figure 1: 184-Pin DIMM (MO-206)
Standard 1.25in. (31.75mm)
Low-Profile 1.15in. (29.21mm)
OPTIONS
MARKING
• Package
184-pin DIMM (standard)
G
1
Y
184-pin DIMM (lead-free)
2
• Memory Clock/Speed, CAS Latency
6ns (167 MHz), 333 MT/s, CL = 2.5
-335
7.5ns (133 MHz), 266 MT/s, CL = 2
-262
1
7.5ns (133 MHz), 266 MT/s, CL = 2
-26A
1
7.5ns (133 MHz), 266 MT/s, CL = 2.5
-265
• PCB
Standard 1.25in. (31.75mm)
See page 2 note
Low-Profile 1.15in. (29.21mm)
See page 2 note
NOTE:
1. Consult Micron for product availability.
2. CL = CAS (READ) Latency
Table 1:
Address Table
128MB
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
1 (S0#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (16 Meg x 8)
1K (A0–A9)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB (x64, SR)
184-PIN DDR SDRAM UDIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
CONFIGURATION
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
MODULE
BANDWITH
2.7GB/s
2.7GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.7GB/s
2.7GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.7GB/s
2.7GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
2.1GB/s
MEMORYCLOCK/
DATA RATE
6ns/333MT/s
6ns/333MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
6ns/333MT/s
6ns/333MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
6ns/333MT/s
6ns/333MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
7.5ns/266MT/s
LATENCY
(CL -
T
RCD -
T
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
PART NUMBER
MT8VDDT1664AG-335__
MT8VDDT1664AY-335__
MT8VDDT1664AG-262__
MT8VDDT1664AY-262__
MT8VDDT1664AG-26A__
MT8VDDT1664AY-26A__
MT8VDDT1664AG-265__
MT8VDDT1664AY-265__
MT8VDDT3264AG-335__
MT8VDDT3264AY-335__
MT8VDDT3264AG-262__
MT8VDDT3264AY-262__
MT8VDDT3264AG-26A__
MT8VDDT3264AY-26A__
MT8VDDT3264AG-265__
MT8VDDT3264AY-265__
MT8VDDT6464AG-335__
MT8VDDT6464AY-335__
MT8VDDT6464AG-262__
MT8VDDT6464AY-262__
MT8VDDT6464AG-26A__
MT8VDDT6464AY-26A__
MT8VDDT6464AG-265__
MT8VDDT6464AY-265__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT8VDDT3264AG-265A1.
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
128MB, 256MB, 512MB (x64, SR)
184-PIN DDR SDRAM UDIMM
Table 3:
Pin Assignment
(184-Pin DIMM Front)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
Q
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
DNU
DNU
V
DD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DNU
A0
DNU
V
SS
DNU
BA1
DQ32
V
DD
Q
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DD
Q
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
CK2#
CK2
V
DD
Q
DQS6
DQ50
DQ51
V
SS
NC
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Table 4:
Pin Assignment
(184-Pin DIMM Back)
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
V
SS
DQ21
A11
DM2
V
DD
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
DD
Q
DM3
A3
DQ30
V
SS
DQ31
DNU
DNU
V
DD
Q
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
DNU
A10
DNU
V
DD
Q
DNU
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
DD
Q
S0#
DNU
DM5
V
SS
DQ46
162 DQ47
163
NC
164 V
DD
Q
165 DQ52
166 DQ53
167
NC
168
V
DD
169 DM6
170 DQ54
171 DQ55
172
V
DD
173
NC
174 DQ60
175 DQ61
176
V
SS
177 DM7
178 DQ62
179 DQ63
180 V
DD
Q
181
SA0
182
SA1
183
SA2
184 V
DDSPD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
93
V
SS
94
DQ4
95
DQ5
96
V
DD
Q
97
DM0
98
DQ6
99
DQ7
100
V
SS
101
NC
102
NC
103
NC
104 V
DD
Q
105 DQ12
106 DQ13
107 DM1
108
V
DD
109 DQ14
110 DQ15
111
DNU
112 V
DD
Q
113
NC
114 DQ20
115
NC/A12
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DD
Q
CK1
CK1#
V
SS
DQ10
DQ11
CKE0
V
DD
Q
DQ16
Pin 115 is “No Connect” for 128MB, “A12” for 256MB and 512MB.
Figure 2: 184-Pin DIMM Pin Locations
Front View
Standard 1.25in. (31.75mm)
U10
Front View
Low-Profile 1.15in. (29.21mm)
U10
U1
U2
U3
U4
U6
U7
U8
U9
U1
U2
U3
U4
U6
U7
U8
U9
PIN 1
PIN 52
PIN 53
PIN 92
PIN 1
PIN 52
PIN 53
PIN 92
Back View
Back View
No Components This Side of Module
U19
U18
U17
U16
U14
U13
U12
U11
PIN 184
PIN 145
PIN 144
PIN 93
PIN 184
PIN 145
PIN 144
PIN 93
Indicates a VDD or VDDQ pin
Indicates a VSS pin
Indicates a VDD or VDDQ pin
Indicates a VSS pin
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
128MB, 256MB, 512MB (x64, SR)
184-PIN DDR SDRAM UDIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#, RAS#
CK0, CK0#, CK1,
CK1#, CK2, CK2#
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read
and write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWER-DOWN. Input buffers (excluding
CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after V
DD
is applied and
until CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Write Mask: DQS9–DQS16 function as DM0–DM7.
DM LOW allows WRITE operation. DM HIGH blocks WRITE
operation. DM lines do not affect READ operation.
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
63, 65, 154
16, 17, 75, 76, 137, 138
21
CKE0
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48,
115
(256MB, 512MB),
118,
122, 125, 130, 141
A0–A11
(128MB)
A0–A12
(256MB, 512MB)
Input
5, 14, 25, 36, 56, 67, 78, 86
DQS0–DQS7
Input/
Output
Input
97, 107, 119, 129, 149, 159,
169, 177
DM0
–
DM7
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
128MB, 256MB, 512MB (x64, SR)
184-PIN DDR SDRAM UDIMM
Table 5:
Pin Descriptions (Continued)
SYMBOL
DQ0–DQ63
TYPE
Input/
Output
Data I/Os: Data bus.
DESCRIPTION
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
2, 4, 6, 8, 12, 13, 19, 20, 23,
24, 28, 31, 33, 35, 39, 40, 53,
55, 57, 60, 61, 64, 68, 69, 72,
73, 79, 80, 83, 84, 87, 88, 94,
95, 98, 99, 105, 106, 109,
110, 114, 117, 121, 123, 126,
127, 131, 133, 146, 147, 150,
151, 153, 155, 161, 162, 165,
166, 170, 171, 174, 175, 178,
179
92
181,182, 183
91
SCL
SA0–SA2
SDA
Input
Input
Input/
Output
Supply
Supply
1
15, 22, 30, 54, 62, 77, 96,
104, 112, 128, 136, 143, 156,
164, 172, 180
7, 38, 46, 70, 85, 108, 120,
148, 168
3, 11, 18, 26, 34, 42, 50, 58,
66, 74, 81, 89, 93, 100, 116,
124, 132, 139, 145, 152, 160,
176
184
44, 45, 47, 49, 51, 111, 134,
135, 140, 142, 144, 158
9, 10, 71, 82, 90, 101, 102,
103, 113, 115 (128MB), 163,
167, 173
V
REF
V
DDQ
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect device.
SSTL_2 reference voltage.
DQ Power Supply: +2.5V ±0.2V.
V
DD
V
SS
Supply
Supply
Power Supply: +2.5V ±0.2V.
Ground.
V
DDSPD
DNU
NC
Supply
—
—
Serial EEPROM positive power supply: +2.3V to +3.6V.
Do Not Use: These pins are not connected on these modules,
but are assigned pins on other modules in this product family.
No Connect: These pins should be left unconnected.
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
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