AS4C512M32MD3-15BCN
HIGH PERFORMANCE 16Gbit LPDDR3 SDRAM
8 BANKS X 32Mbit X 32 X 2 CS
Specifications
-
Density : 16G bits
-
Organization :
- 32M words x 32 bits x 8 banks x 2 CS
-
Package :
- 178-ball FBGA
- Lead-free (RoHS compliant) and Halogen-free
Power supply :
- VDD1 = 1.8V (1.7V~1.95V)
- VDD2/VDDQ/VDDCA = 1.2V (1.14V~1.3V)
HSUL_12 interface (High Speed Unterminated Logic
1.2V)
Data rate :
- 1333Mbps RL=10
RL / WL select setA / setB
Driver strength :
- Typical : 34.3/40/48/60/80
Ω
- PD34.3_PU40 / PD40_PU48 / PD34.3_PU48
ODT: RZQ/4, RZQ/2, RZQ/1 (RZQ = 240
Ω)
Operating case temperature range
- Commercial Tc = -25°C to +85°C
-
-
-
-
-
-
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Features
-
Low power consumption
-
Eight-bit prefetch DDR architecture and BL8 only
-
Eight internal banks for concurrent operation
-
Double data rate architecture for command, address
and data Bus
-
Bidirectional and differential data strobe per byte of
data (DQS and DQS)
-
DQS is edge-aligned with data for READs, center-
aligned with data for WRITEs
-
Differential clock inputs (CK and CK)
-
Data mask (DM) for write data
-
Programmable READ and WRITE latencies (RL/WL)
-
Auto Refresh and Self Refresh
-
Per-bank refresh for concurrent operation
-
Partial-array self refresh (PASR)
-
On-chip temperature sensor to control self refresh rate
for temperature compensated self refresh (TCSR)
-
Deep power-down mode (DPD)
-
Selectable output drive strength (DS)
-
Selectable On-Die Termination
-
CA Training
-
Write leveling via MR setting
-
Clock stop capability
-
DQ calibration offering specific DQ output patterns
-
ZQ calibration
Table 1. Ordering Information
Product part No
Org
Temperature
Max Clock (MHz)
667
Package
178-ball
FBGA
AS4C512M32MD3-15BCN 512M
x
32
Commercial
-25°C
to
+85°C
Table 2. Speed Grade Information
Speed Grade
LPDDR3-1333
Clock Frequency
667
MHz
Read latency (RL)
10
Write Latency (Set A)
Clock Cycle Time (tCK)
6
1.5
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AS4C512M32MD3-15BCN
Signal Pin Description
Pin
CK, CK
(CK_t, CK_c)
CKE
Type
Input
Function
Clock :
CK and CK are differential clock inputs. All CA inputs are sampled on both rising and falling
edges of CK. CS and CKE inputs are sampled at the rising edge of CK. AC timings are referenced
to clock.
Clock Enable :
CKE HIGH activates and CKE LOW deactivates the internal clock signals, input
buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions. CKE is
considered part of the command code. CKE is sampled at the rising edge of CK.
Chip Select :
CS is considered part of the command code and is sampled at the rising edge of CK.
Command/address inputs:
Provide the command and address inputs according to the
command truth table.
Input Data Mask :
DM is an input mask signal for write data. Although DM balls are input-only, the
DM loading is designed to match that of DQ and DQS balls. DM[3:0] is DM for each of the four data
bytes, respectively.
Input
CS(CS_n)
CA0~CA9
DM0~DM3
Input
Input
Input
DQ0~DQ31
DQS[3:0],
(DQS_t[3:0]),
DQS[3:0]
(DQS_c[3:0])
NC
ODT
ZQ
VDD1
VDD2
VDDQ
VDDCA
VREF(DQ),
VREF(CA)
VSS
VSSQ
VSSCA
Input/output
Data input/output:
Bidirectional data bus.
Input/output
Data strobe:
The data strobe is bidirectional (used for read and write data) and complementary
(DQS and DQS). It is edge-aligned output with read data and centered input with write data.
DQS[3:0]/DQS[3:0] is DQS for each of the four data bytes, respectively
No Connect:
No internal electrical connection is present.
Input
Input
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
On-Die Termination:
This signal enables and disables termination on the DRAM DQ bus according
to the specified mode register setting.
External impedance (240 ohm):
This signal is used to calibrate the device out-put impedance.
Core power:
Supply 1.
Core power:
Supply 2.
DQ power supply:
Isolated on the die for improved noise immunity.
Command/address power supply:
Command/address power supply.
Reference voltage:
VREF(CA) is reference for command/address input buffers,VREF(DQ) is refer-
ence for DQ input buffers.
Common ground
DQ Common ground
CA Common ground
Confidential
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Rev.1.1 Aug. 2017
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