IR3081PBF
DATA SHEET
XPHASE
TM
VR 10 CONTROL IC
DESCRIPTION
The IR3081PBF Control IC combined with an IR
XPhase
TM
Phase IC provides a full featured and flexible
way to implement a complete VR 10 power solution. The “Control” IC provides overall system control and
interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a multiphase
converter. The XPhase
TM
architecture results in a power supply that is smaller, less expensive, and easier
to design while providing higher efficiency than conventional approaches.
The IR3081PBF is intended for VRD or VRM/EVRD 10 applications that use external VCCVID/VTT
circuits.
FEATURES
•
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•
•
•
•
•
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•
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6 bit VR 10 compatible VID with 0.5% overall system accuracy
1 to X phases operation with matching phase ICs
Programmable Dynamic VID Slew Rate
No Discharge of output capacitors during Dynamic VID step-down (can be disabled)
+/-300mV Differential Remote Sense
Programmable 150kHz to 1MHz oscillator
Programmable VID Offset and Load Line output impedance
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Powergood provides indication of proper operation and avoids false triggering
Operates from 12V input with 9.1V Under-Voltage Lockout
6.8V/5mA Bias Regulator provides System Reference Voltage
Enable Input
Small thermally enhanced 28L MLPQ package
PACKAGE PINOUT
28
27
26
25
ENABLE
PWRGD
24
LGND
23
SS/DEL
RMPOUT
VCC
N/C
22
1
2
3
4
5
6
7
OSCDS
VID5
VID0
VID1
VID2
VID3
VBIAS
BBFB
21
20
19
18
17
16
15
IR3081
CONTROL
IC
VOSNS-
EAOUT
FB
VDRP
IIN
OCSET
VID4
TRM1
TRM2
TRM3
TRM4
ROSC
13
11
Page 1 of 40
10
12
14
8
9
VDAC
10/01
/04
IR3081PBF
ORDERING INFORAMATION
Device
IR3081MPBFTR
IR3081MPBF
Order Quantity
3000 per reel
100 piece strips
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature……………..150
o
C
Storage Temperature Range………………….-65
o
C to 150
o
C
ESD Rating………………………………………HBM Class 1C JEDEC standard
PIN #
1
2-7
8, 9,
11,12
10
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
OSCDS
VID0-5
TRM1-4
VOSNS-
ROSC
VDAC
OCSET
IIN
VDRP
FB
EAOUT
BBFB
VBIAS
VCC
LGND
RMPOUT
SS/DEL
PWRGD
N/C
ENABLE
V
MAX
20V
20V
Do Not Connect
0.5V
20V
20V
20V
20V
20V
20V
10V
20V
20V
20V
n/a
20V
20V
20V
n/a
20V
V
MIN
-0.3V
-0.3V
Do Not Connect
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
-0.3V
-0.3V
-0.3V
n/a
-0.3V
I
SOURCE
1mA
10mA
Do Not Connect
10mA
1mA
1mA
1mA
1mA
5mA
1mA
10mA
1mA
1mA
1mA
50mA
1mA
1mA
1mA
n/a
1mA
I
SINK
1mA
10mA
Do Not Connect
10mA
1mA
1mA
1mA
1mA
5mA
1mA
20mA
1mA
1mA
50mA
1mA
1mA
1mA
20mA
n/a
1mA
Page 2 of 40
10/01
/04
IR3081PBF
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 9.5V
≤
V
CC
≤
14V, 0
o
C
≤
T
J
≤
100
o
C
PARAMETER
VDAC Reference
System Set-Point Accuracy
TEST CONDITION
-0.3V
≤
VOSNS-
≤
0.3V, Connect FB to
EAOUT, Measure V(EAOUT) –
V(VOSNS-) deviation from Table 1.
Applies to all VID codes.
R
ROSC
= 41.9kΩ
R
ROSC
= 41.9kΩ
0V
≤
VID0-5
≤
VCC
MIN
TYP
0.5
MAX
UNIT
%
Source Current
Sink Current
VID Input Threshold
VID Input Bias Current
Regulation Detect Comparator
Input Offset
Regulation Detect to EAOUT
Delay
BBFB to FB Bias Current
Ratio
VID 11111x Blanking Delay
VID Step Down Detect
Blanking Time
VID Down BB Clamp Voltage
VID Down BB Clamp Current
Error Amplifier
Input Offset Voltage
68
47
500
-5
-5
80
55
600
0
0
130
92
63
700
5
5
200
1.05
μA
μA
mV
μA
mV
ns
μA/μA
ns
μs
0.95
Measure Time till PWRGD drives low
Measure from VID inputs to EAOUT
Percent of VDAC voltage
70
3.5
-3
1.00
800
1.7
75
6.2
4
80
12
8
%
mA
mV
FB Bias Current
DC Gain
Gain-Bandwidth Product
Source Current
Sink Current
Max Voltage
Min Voltage
VDRP Buffer Amplifier
Input Offset Voltage
Input Voltage Range
Bandwidth (-3dB)
Slew Rate
IIN Bias Current
Connect FB to EAOUT, Measure
V(EAOUT) – V(DAC). from Table 1.
Applies to all VID codes and -0.3V
≤
VOSNS-
≤
0.3V. Note 2
R
ROSC
= 41.9kΩ
Note 1
Note 1
VBIAS–VEAOUT (referenced to VBIAS)
Normal operation or Fault mode
V(VDRP) – V(IIN), 0.8V
≤
V(IIN)
≤
5.5V
Note 1
-31
90
4
0.4
0.7
125
30
-8
0.8
1
-2.0
-29.5
100
7
0.6
1.2
250
100
0
6
10
-0.75
-28
105
0.8
1.7
375
150
8
5.5
μA
dB
MHz
mA
mA
mV
mV
mV
V
MHz
V/μs
μA
0
Page 3 of 40
10/01
/04
IR3081PBF
PARAMETER
Oscillator
Switching Frequency
Peak Voltage (5V typical,
measured as % of VBIAS)
Valley Voltage (1V typical,
measured as % of VBIAS)
VBIAS Regulator
Output Voltage
Current Limit
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
Charge Current
Discharge Current
Charge/Discharge Current
Ratio
Charge Voltage
Delay Comparator Threshold
Discharge Comparator
Threshold
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
PWRGD Output
Output Voltage
Leakage Current
Enable Input
Threshold voltage
Bias Current
VCC Under-Voltage Lockout
Start Threshold
Stop Threshold
Hysteresis
General
VCC Supply Current
VOSNS- Current
TEST CONDITION
R
ROSC
= 41.9kΩ
R
ROSC
= 41.9kΩ
R
ROSC
= 41.9kΩ
MIN
255
70
11
TYP
300
71
14
MAX
345
74
16
UNIT
kHz
%
%
-5mA
≤
I(VBIAS)
≤
0
6.5
-30
0.85
40
4
10
3.7
70
150
6.8
-15
1.3
70
6
11.5
4.0
90
200
7.1
-6
1.5
100
9
13
4.2
110
250
V
mA
V
μA
μA
μA/μA
V
mV
mV
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
Relative to Charge Voltage
1V
≤
V(OCSET)
≤
5V
R
ROSC
= 41.9kΩ
I(PWRGD) = 4mA
V(PWRGD) = 5.5V
-10
-31
0
-29.5
150
0
10
-28
400
10
700
5
9.6
9.4
300
14
-3.5
mV
μA
mV
μA
mV
μA
V
V
mV
mA
mA
0V
≤
V(ENABLE)
≤
VCC
500
-5
8.6
8.4
150
8
-5.5
600
0
9.1
8.9
200
11
-4.5
Start – Stop
-0.3V
≤
VOSNS-
≤
0.3V, All VID Codes
Note 1:
Guaranteed by design, but not tested in production
Note 2:
VDAC Output is trimmed to compensate for Error Amplifier input offsets errors
Page 4 of 40
10/01
/04
IR3081PBF
PIN DESCRIPTION
PIN#
1
2-7
8, 9,
11,12
10
13
14
PIN SYMBOL
OSCDS
VID0-5
TRM1-4
VOSNS-
ROSC
VDAC
15
OCSET
16
17
18
IIN
VDRP
FB
19
20
EAOUT
BBFB
21
22
23
24
25
VBIAS
VCC
LGND
RMPOUT
SS/DEL
26
27
28
PWRGD
N/C
ENABLE
PIN DESCRIPTION
Apply a voltage greater than VBIAS to disable the oscillator. Used during factory
testing & trimming. Ground or leave open for normal operation.
Inputs to VID D to A Converter
Used for precision post-package trimming of the VDAC voltage. Do not make any
connection to these pins.
Remote Sense Input. Connect to ground at the Load.
Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET,
BBFB, and VDAC bias currents
Regulated voltage programmed by the VID inputs. Current Sensing and PWM
operation are referenced to this pin. Connect an external RC network to VOSNS- to
program Dynamic VID slew rate.
Programs the hiccup over-current threshold through an external resistor tied to
VDAC and an internal current source. Over-current protection can be disabled by
connecting this pin to a DC voltage no greater than 6.5V (do not float this pin as
improper operation will occur).
Current Sense input from the Phase IC(s). To ensure proper operation bias to at
least 250mV (don’t float this pin).
Buffered IIN signal. Connect an external RC network to FB to program converter
output impedance
Inverting input to the Error Amplifier. Converter output voltage is offset from the
VDAC voltage through an external resistor connected to the converter output voltage
at the load and an internal current source.
Output of the Error Amplifier
Input to the Regulation Detect Comparator. Connect to converter output voltage and
VDRP pin through resistor network to program recovery from VID step-down.
Connect to ground to disable Body Braking
TM
during transition to a lower VID code.
6.8V/5mA Regulated output used as a system reference voltage for internal circuitry
and the Phase ICs.
Power for internal circuitry
Local Ground and IC substrate connection
Oscillator Output voltage. Used by Phase ICs to program Phase Delay
Controls Converter Softstart, Power Good, and Over-Current Delay Timing. Connect
an external capacitor to LGND to program the timing. An optional resistor can be
added in series with the capacitor to reduce the over-current delay time.
Open Collector output that drives low during Softstart and any external fault
condition. Connect external pull-up.
No internal connection
Enable Input. A logic low applied to this pin puts the IC into Fault mode.
Page 5 of 40
10/01
/04
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