Electronics, Inc.
2590 North First Street, San Jose, CA 95131, U.S.A.
Tel: 408-732-5000
Fax: 408-732-5055
http://www.atpinc.com
Rev
. Date:
Nov. 26, 2015
ATP AQ12M72D8BLK0M
4GB DDR3-1600 UNBUFFERED ECC DIMM
DESCRIPTION
The ATP AQ12M72D8BLK0M is a high performance 4GB DDR3-1600 Unbuffered ECC SDRAM memory
module. It is organized as 512M x 72 in a 240-pin Dual-In-Line Memory Module (DIMM) package. The
module utilizes nine 512Mx8 DDR3 SDRAMs in FBGA package. The module consists of a 256-byte serial
EEPROM, which contains the module configuration information.
KEY FEATURES
Density:
4GB (512M x 72)
DIMM Rank:
1 Rank
Cycle Time:
1.25ns (800MHz)
CAS Latency: 11
Power supply: 1.5V ± 0.075V
Internal self calibration through ZQ
Burst lengths:
8
2
On-board I C temperature sensor with
integrated (SPD) EEPROM
Auto & Self refresh
Part No.
AQ12M72D8BLK0M
PIN DESCRIPTION
Pin Name
A0~A9, A11~A15
A10/AP
BA0~BA2
CAS
CB0~CB7
CK0
Asynchronous Reset
Minimum Thickness of Golden Finger: 30
Micro-inch
7.8
s
refresh interval at lower than T
CASE
85°C, 3.9s refresh interval at 85°C < T
CASE
< 95 °C
Dynamic On Die Termination
Fly-by topology
PCB Height: 1.18 inches
RoHS compliant
Interface
SSTL_1.5
Max Freq
800MHz (1.25ns@CL=11) x2
Pin Name
ODT0
VTT
RAS
RESET
WE
CS0
SA0~SA2
SCL
SDA
RSVD
VDD
VDDQ
VDDSPD
VSS
TEST
Description
SDRAM Address Bus
Address Input/Auto precharge
SDRAM Bank Select
Column Address Strobe
DIMM ECC Check bits
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enables
Data Masks
Temperature sensor Event output
Data Input/Output
Data strobes/ high data strobes
Data strobes(negative line)
Input/Output Reference supply
Command/address reference supply
No Connect
Description
On die termination
SDRAM I/O termination supply
Row Address Strobe
Set DRAMs to Known State
Write Enable
Chip Selects
2
I C serial bus data line for EEPROM
2
I C serial bus clock for EEPROM
2
I C slave address select for EEPROM
Reserved for Future Use
Core Power
I/O Driver Power
SPD Power
Ground
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
CK0
CKE0
DM0~DM8
Event
DQ0~DQ63
DQS0~DQS8
DQS0 ~
DQS8
VREFDQ
VREFCA
NC
Your Ultimate Memory Solution!
Page 1 of 7
ATP AQ12M72D8BLK0M
ABSOLUTE MAXIMUM DC RATINGS
Item
Voltage on V
DD
pin relative to V
SS
Voltage on V
DDQ
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage Temperature
Operating Temperature
Symbol
V
DD
V
DDQ
V
IN
, V
OUT
T
STG
T
CASE
Rating
-0.4V ~ 1.975V
-0.4V ~ 1.975V
-0.4V ~ 1.975V
-55 to +100
0 to +95
Units
V
V
V
o
C
o
C
Notes
1
1
1
1
1,2,3
Note:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. It is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. At 85 - 95
o
C operation temperature range, doubling refresh commands in frequency to a 32ms period ( Refresh interval =3.9 µs ) is required, and to enter
to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
AC & DC OPERATING CONDITIONS (SSTL- 15)
Recommended operating conditions
Item
Supply Voltage
Supply Voltage for Output
4
V
REF
CA
(DC)
V
REF
DQ
(DC)
Input High Voltage (DC)
Input High Voltage (AC)
Input Low Voltage (DC)
Input Low Voltage (AC)
Symbol
V
DD
V
DDQ
I/O
I/O
V
IH
(DC)
V
IH
(AC)
V
IL
(DC)
V
IL
(AC)
Min.
1.425
1.425
0.49 * V
DDQ
0.49 * V
DDQ
V
REF
+ 0.100
V
REF
+ 0.150
V
SS
-
Typical
1.5
1.5
0.50 * V
DDQ
0.50 * V
DDQ
-
-
-
-
Max.
1.575
1.575
0.51 * V
DDQ
0.51 * V
DDQ
V
DD
-
V
REF
- 0.100
V
REF
- 0.150
Units
V
V
V
V
V
V
V
V
Note:
1. The value of V
REF
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
REF
is expected to be about 0.5 x
V
DDQ
of the transmitting device and V
REF
is expected to track variations in V
DDQ
.
2. Peak to peak AC noise on V
REF
may not exceed
2%
V
REF
(DC).
3. V
TT
of transmitting device must track V
REF
of receiving device.
4. AC parameters are measured with V
DD
, V
DDQ
and V
DDL
tied together.
RELIABILITY
MTBF @25
o
C (Hours)
1
10,979,000
FIT @ 25
o
C
2
91
MTBF @40
o
C (Hours)
1
5,901,000
FIT @ 40
o
C
2
169
Note:
1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual
components in the module. It assumes nominal voltage, with all other parameters within specified range.
2. Failures per Billion Device-Hours
Your Ultimate Memory Solution!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 4 of 7
ATP AQ12M72D8BLK0M
IDD SPECIFICATION PARAMETER & POWER CONSUMPTION
(IDD values are for full operating range of Voltage and Temperature)
Symbol
IDD0
Proposed Conditions
Operating one bank active-precharge current;
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Timing table ; BL: 8; AL: 0;/ CS: High between ACT and PRE;
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with
one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Value
260
Units
mA
Operating one bank active-read-precharge current;
IDD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Timing table ; BL: 8; AL: 0; /CS: High between ACT, RD and
PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
390
mA
Precharge Power-Down Current Slow Exit
IDD2P0
CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address
Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2); ODT Signal: stable at 0; Pre-charge Power Down Mode: Slow Exit
90
mA
Precharge Power-Down Current Fast Exit
IDD2P1
CKE: Low; External clock: On; tCK, CL: see Timing table; BL: 81); AL: 0; /CS: stable at 1; Command, Address, Bank Address
Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Fast Exit
100
mA
Precharge standby current;
IDD2N
CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address
Inputs: partially tog-gling; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers; ODT Signal: stable at 0;
150
mA
Precharge Standby ODT Current
IDD2NT
CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address
Inputs: partially tog-gling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers
180
mA
Precharge quiet standby current;
IDD2Q
CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address
Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
140
mA
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address
Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
140
mA
Active Standby Current
IDD3N
CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address
Inputs: partially tog-gling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled
in Mode Registers; ODT Signal: stable at 0;
180
mA
Operating Burst Read Current
IDD4R
CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: High between RD; Command, Address, Bank
Address Inputs: par-tially toggling ; Data IO: seamless read data burst with different data between one burst and the next one;
DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT:
Enabled in Mode Registers; ODT Signal: stable at 0;
810
mA
Operating Burst Write Current
IDD4W
CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; CS: High between WR; Command, Address, Bank
Address Inputs: par-tially toggling ; Data IO: seamless write data burst with different data between one burst and the next one;
DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT:
Enabled in Mode Registers; ODT Signal: stable at HIGH;
910
mA
Burst Refresh Current
IDD5B
CKE: High; External clock: On; tCK, CL, nRFC: see Timing table ; BL: 8; AL: 0; CS: High between REF; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC;
Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
1,370
mA
Self Refresh Current: Normal Temperature Range TCASE:
0 - 85°C;
IDD6
Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK
and CK: LOW; CL: see Timing table ; BL: 8; AL: 0; /CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable
at 0; Bank Activity: Self- Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
140
mA
Operating Bank Interleave Read Current
IDD7
PDIMM
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Timing table ; BL: 8; AL: CL-1; /CS: High
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling; Data IO: read data bursts with different
data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0,
1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
1,170
2,060
mA
Power Consumption per DIMM
System is operating at 800 MHz clock with VDD = 1.5V. This parameter is calculated at a common loading.
mW
Your Ultimate Memory Solution!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 5 of 7
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