Junction Temperature ......................................................+125°C
Storage Temperature Range .............................-55°C to +125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C.)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
Input Low Voltage
Input High Voltage
Output Low Voltage at 4mA
Operating Charge
Recovery Time
Time Slot Duration
Reset Low Time
Reset High Time
Presence-Detect High Time
Presence-Detect Low Time
Presence-Detect Sample Time
IO PIN: 1-Wire WRITE
Write-Zero Low Time
Write-One Low Time
IO PIN: 1-Wire READ
Read Low Time
Read Sample Time
t
RL
t
MSR
(Notes 3, 15)
(Notes 3, 15)
1
t
RL
+
15 -
15
μs
μs
t
W0L
t
W1L
(Notes 3, 14)
(Notes 3, 14)
60
1
120
15
μs
μs
V
PUP
R
PUP
C
IO
I
L
V
IL
V
IH
V
OL
Q
OP
t
REC
t
SLOT
t
RSTL
t
RSTH
t
PDH
t
PDL
t
MSP
(Note 13)
(Note 3)
(Notes 1, 2)
(Notes 3, 4)
(Notes 5, 6)
(Note 7)
(Notes 1, 3, 8)
(Notes 1, 9)
(Note 1)
(Notes 6, 10)
(Note 3)
(Note 3)
(Notes 3, 11)
(Notes 3, 12)
1
61
480
480
15
60
60
60
240
75
30
2.2
0.4
2.8
0.6
100
0.25
0.3
6.0
5
800
V
k
pF
μA
V
V
V
nC
μs
μs
μs
μs
μs
μs
μs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
All voltages are referenced to ground.
External pullup voltage. See Figure 4.
System requirement.
Full R
PUP
range is guaranteed by design and simulation and not production tested. Production testing performed at a
fixed R
PUP
value. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-
Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recov-
ery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required.
Capacitance on the IO pin could be 800pF when power is first applied. If a 5kΩ resistor is used to pull up the IO line to
V
PUP
, 5µs after power has been applied the parasite capacitance will not affect normal communications.
Guaranteed by design, simulation only. Not production tested.
Input load is to ground.
2
Maxim Integrated
DS1990A
Serial Number iButton
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
The voltage on IO must be less than or equal to V
ILMAX
whenever the master drives the line low.
V
IH
is a function of the internal supply voltage.
30nC per 72 time slots at 5.0V pullup voltage with a 5kΩ pullup resistor and t
SLOT
≤
120µs.
The reset low time (t
RSTL
) should be restricted to a maximum of 960µs to allow interrupt signaling. A longer duration could
mask or conceal interrupt pulses if this device is used in parallel with a DS1994.
An additional reset or communication sequence cannot begin until the reset high time has expired.
Presence pulse is guaranteed only after a preceding reset pulse (t
RSTL
).
ε
in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
IH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
-
ε
and t
W0LMAX
+ t
F
-
ε,
respectively.
δ
in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
iButton CAN PHYSICAL SPECIFICATION
SIZE
WEIGHT (DS1990A)
See the
Package Information
section.
Ca. 2.5 grams
Detailed Description
The block diagram in Figure 1 shows the major function
blocks of the device. The DS1990A takes the energy it
needs to operate from the IO line, as indicated by the
parasite power block. The ROM function control unit
includes the 1-Wire interface and the logic to implement
the ROM function commands, which access 64 bits of
lasered ROM.
PARASITE POWER
DS1990A
IO
ROM
FUNCTION CONTROL
64-BIT
LASERED ROM
Figure 1. Block Diagram
Maxim Integrated
3
DS1990A
Serial Number iButton
64-Bit Lasered ROM
Each DS1990A contains a unique ROM code that is 64
bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits
are a CRC of the first 56 bits. See Figure 2 for details.
The 1-Wire CRC is generated using a polynomial gen-
erator consisting of a shift register and XOR gates as
shown in Figure 3. The polynomial is X
8
+ X
5
+ X
4
+ 1.
Additional information about the 1-Wire Cyclic
Redundancy Check (CRC) is available in Application
Note 27:
Understanding and Using Cyclic Redundancy
Checks with Maxim iButton Products.
The shift register bits are initialized to 0. Then starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the 48th bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of CRC returns the shift register to all 0s.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS1990A
is a slave device. The bus master is typically a micro-
controller or PC. For small configurations, the 1-Wire
communication signals can be generated under soft-
ware control using a single port pin. Alternatively, the
DS2480B 1-Wire line driver chip or serial-port adapters
based on this chip (DS9097U series) can be used. This
simplifies the hardware design and frees the micro-
processor from responding in real time. The discussion
of this bus system is broken down into three topics:
hardware configuration, transaction sequence, and
1-Wire signaling (signal types and timing). The 1-Wire
protocol defines bus transactions in terms of the bus
state during specific time slots that are initiated on the
falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of
the
Book of iButton Standards.
MSB
8-BIT
CRC CODE
MSB
LSB MSB
48-BIT SERIAL NUMBER
LSB MSB
8-BIT FAMILY CODE
(01h)
LSB
LSB
Figure 2. 64-Bit Lasered ROM
POLYNOMIAL = X
8
+ X
5
+ X
4
+ 1
1ST
STAGE
X
0
X
1
2ND
STAGE
X
2
3RD
STAGE
X
3
4TH
STAGE
X
4
5TH
STAGE
X
5
6TH
STAGE
X
6
7TH
STAGE
X
7
8TH
STAGE
X
8
INPUT DATA
Figure 3. 1-Wire CRC Generator
4
Maxim Integrated
DS1990A
Serial Number iButton
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS1990A is
open drain with an internal circuit equivalent to that
shown in Figure 4. A multidrop bus consists of a 1-Wire
bus with multiple slaves attached. At standard speed,
the 1-Wire bus has a maximum data rate of 16.3kbps.
The value of the pullup resistor primarily depends on
the network size and load conditions. For most applica-
tions, the optimal value of the pullup resistor is approxi-
mately 2.2kΩ. The idle state for the 1-Wire bus is high.
If for any reason a transaction needs to be suspended,
the bus
must
be left in the idle state if the transaction is
to resume. If this does not occur and the bus is left low
for more than 120µs, one or more devices on the bus
may be reset.
Transaction Sequence
The protocol for accessing the DS1990A through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
Initialization
All transactions on the 1-Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s). The
presence pulse lets the bus master know that the
DS1990A is on the bus and is ready to operate. For
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