FEATURES ............................................................................................................................................................. 5
BUS OPERATION ................................................................................................................................................. 11
Table 2-1. BUS OPERATION ...................................................................................................................... 11
Table 2-2. BUS OPERATION ...................................................................................................................... 12
Figure 16. SILICON ID READ TIMING WAVEFORM .................................................................................. 54
WRITE OPERATION STATUS .............................................................................................................................. 55
Figure 21. TOGGLE BIT ALGORITHM........................................................................................................ 59
Figure 22. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to
word mode) ................................................................................................................................................. 60
At Device Power-Up .................................................................................................................................... 64
Figure A. AC Timing at Device Power-Up.................................................................................................... 64
ERASE AND PROGRAMMING PERFORMANCE ............................................................................................... 65
DATA RETENTION ............................................................................................................................................... 65
ORDERING INFORMATION ................................................................................................................................. 66
PART NAME DESCRIPTION ................................................................................................................................ 67
PACKAGE INFORMATION ................................................................................................................................... 68
REVISION HISTORY ............................................................................................................................................ 71
P/N:PM1683
REV. 1.5, AUG. 24, 2015
4
MX29GL128F
SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
- MX29GL128F H/L: VI/O=VCC=2.7V~3.6V, VI/O voltage must tight with VCC
- MX29GL128F U/D: VI/O=1.65V~3.6V for Input/Output
• Byte/Word mode switchable
- 16,777,216 x 8 / 8,388,608 x 16
• 64KW/128KB uniform sector architecture
- 128 equal sectors
• 16-byte/8-word page read buffer
• 64-byte/32-word write buffer
• Extra 128-word sector for security
- Features factory locked and identifiable, and customer lockable
• Advanced sector protection function (Solid and Password Protect)
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc ≤ VLKO
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
• Deep power down mode
PERFORMANCE
• High Performance
- Fast access time:
- MX29GL128F H/L: 70/90ns (VCC=2.7~3.6V)
- MX29GL128F U/D: 90/110ns (VCC=2.7~3.6V, V I/O=1.65V to Vcc)
- Page access time:
- MX29GL128F H/L: 25ns
- MX29GL128F U/D: 30ns
- Fast program time: 10us/word
- Fast erase time: 0.5s/sector
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 20uA (typical)
•
Minimum 100,000 erase/program cycle
• 20 years data retention
SOFTWARE FEATURES
• Program/Erase Suspend & Program/Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
- Suspends sector program operation to read data from another sector which is not being program
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Hardware write protect pin/Provides accelerated program capability
Frame check sequence: 4-byte field that contains the cyclic redundancy check (CRC)value. The CRC computation is based on the following fields: source address,
destination address, ......
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