MX25U3235F
MX25U3235F
1.8V, 32M-BIT [x 1/x 2/x 4]
CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Fast Program and Erase time
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Quad Peripheral Interface (QPI) Read / Program Mode
• Program Suspend/Resume & Erase Suspend/Resume
P/N: PM1977
1
Rev. 1.6, July 12, 2017
MX25U3235F
Contents
1. FEATURES .............................................................................................................................................................. 5
2. GENERAL DESCRIPTION ..................................................................................................................................... 6
Table 1. Additional Feature..........................................................................................................................7
3. PIN CONFIGURATIONS ......................................................................................................................................... 8
4. PIN DESCRIPTION .................................................................................................................................................. 8
5. BLOCK DIAGRAM................................................................................................................................................... 9
6. DATA PROTECTION.............................................................................................................................................. 10
Table 2. Protected Area Sizes ................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition
....................................................................................................12
7. MEMORY ORGANIZATION ................................................................................................................................... 13
Table 4. Memory Organization ..................................................................................................................13
8. DEVICE OPERATION ............................................................................................................................................ 14
8-1. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 16
9. COMMAND DESCRIPTION ................................................................................................................................... 17
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
9-23.
9-24.
P/N: PM1977
Table 5. Command Set..............................................................................................................................17
Write Enable (WREN) .............................................................................................................................. 21
Write Disable (WRDI)............................................................................................................................... 22
Read Identification (RDID)
....................................................................................................................... 23
Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 24
Read Electronic Manufacturer ID & Device ID (REMS) ........................................................................... 26
QPI ID Read (QPIID) ............................................................................................................................... 27
Table 6. ID Definitions
..............................................................................................................................27
Read Status Register (RDSR) ................................................................................................................. 28
Table 7. Status Register ............................................................................................................................31
Write Status Register (WRSR)................................................................................................................. 32
Table 8. Protection Modes.........................................................................................................................33
Read Data Bytes (READ) ........................................................................................................................ 36
Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 37
Dual Read Mode (DREAD) ...................................................................................................................... 39
2 x I/O Read Mode (2READ) ................................................................................................................... 40
Quad Read Mode (QREAD) .................................................................................................................... 41
4 x I/O Read Mode (4READ) ................................................................................................................... 42
Burst Read ............................................................................................................................................... 45
Performance Enhance Mode ................................................................................................................... 46
Sector Erase (SE) .................................................................................................................................... 49
Block Erase (BE32K) ............................................................................................................................... 50
Block Erase (BE) ..................................................................................................................................... 51
Chip Erase (CE) ....................................................................................................................................... 52
Page Program (PP) ................................................................................................................................. 53
4 x I/O Page Program (4PP) .................................................................................................................... 55
Deep Power-down (DP) ........................................................................................................................... 56
Enter Secured OTP (ENSO) .................................................................................................................... 57
Rev. 1.6, July 12, 2017
2
MX25U3235F
9-25. Exit Secured OTP (EXSO) ....................................................................................................................... 57
9-26. Read Security Register (RDSCUR) ......................................................................................................... 57
Table 9. Security Register Definition
.........................................................................................................58
9-27. Write Security Register (WRSCUR)......................................................................................................... 58
9-28. Write Protection Selection (WPSEL)........................................................................................................ 59
9-29. Single Block Lock/Unlock Protection (SBLK/SBULK) .............................................................................. 62
9-30. Read Block Lock Status (RDBLOCK) ...................................................................................................... 64
9-31. Gang Block Lock/Unlock (GBLK/GBULK) ............................................................................................... 64
9-32. Program Suspend and Erase Suspend ................................................................................................... 65
Table 10. Readable Area of Memory While a Program or Erase Operation is Suspended .......................65
Table 11. Acceptable Commands During Suspend after tPSL/tESL .........................................................66
Table 12. Acceptable Commands During Suspend (tPSL/tESL not required) ...........................................66
9-33. Program Resume and Erase Resume ..................................................................................................... 68
9-34. No Operation (NOP) ................................................................................................................................ 69
9-35. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 69
9-36. Read SFDP Mode (RDSFDP).................................................................................................................. 71
Table 13. Signature and Parameter Identification Data Values
................................................................72
Table 14. Parameter Table (0): JEDEC Flash Parameter Tables ..............................................................73
Table 15. Parameter Table (1): Macronix Flash Parameter Tables ...........................................................75
10. RESET.................................................................................................................................................................. 77
Table 16. Reset Timing..............................................................................................................................77
11. POWER-ON STATE ............................................................................................................................................. 78
12. ELECTRICAL SPECIFICATIONS ........................................................................................................................ 79
Table 17. Absolute Maximum Ratings .......................................................................................................79
Table 18. Capacitance...............................................................................................................................79
Table 19. DC Characteristics.....................................................................................................................81
Table 20. AC Characteristics ....................................................................................................................82
13. OPERATING CONDITIONS ................................................................................................................................. 84
Table 21. Power-Up Timing and VWI Threshold
.......................................................................................86
13-1. Initial Delivery State ................................................................................................................................. 86
14. ERASE AND PROGRAMMING PERFORMANCE .............................................................................................. 87
15. LATCH-UP CHARACTERISTICS ........................................................................................................................ 87
16. ORDERING INFORMATION ................................................................................................................................ 88
17. PART NAME DESCRIPTION ............................................................................................................................... 89
18. PACKAGE INFORMATION .................................................................................................................................. 90
18-1. 8-pin SOP (200mil) .................................................................................................................................. 90
18-2. 8-land WSON (6x5mm)............................................................................................................................ 91
18-3. 8-land USON (4x3mm) ............................................................................................................................ 92
18-4. 8-land XSON(4x4mm) ............................................................................................................................. 93
18-5. 12-ball WLCSP ........................................................................................................................................ 94
19. REVISION HISTORY ........................................................................................................................................... 95
P/N: PM1977
3
Rev. 1.6, July 12, 2017
MX25U3235F
Figures
Figure 1. Serial Modes Supported ...............................................................................................................................................14
Figure 2. Serial Input Timing ........................................................................................................................................................15
Figure 3. Output Timing ...............................................................................................................................................................15
Figure 4. Enable QPI Sequence (Command 35h) .......................................................................................................................16
Figure 5. Reset QPI Mode (Command F5h) ................................................................................................................................16
Figure 6. Write Enable (WREN) Sequence (SPI Mode) ..............................................................................................................21
Figure 7. Write Enable (WREN) Sequence (QPI Mode) ..............................................................................................................21
Figure 8. Write Disable (WRDI) Sequence (SPI Mode) ...............................................................................................................22
Figure 9. Write Disable (WRDI) Sequence (QPI Mode)...............................................................................................................22
Figure 10. Read Identification (RDID) Sequence (SPI mode only)
..............................................................................................23
Figure 11. Read Electronic Signature (RES) Sequence (SPI Mode) ...........................................................................................24
Figure 12. Read Electronic Signature (RES) Sequence (QPI Mode) ..........................................................................................25
Figure 13. Release from Deep Power-down (RDP) Sequence (SPI Mode) ................................................................................25
Figure 14. Release from Deep Power-down (RDP) Sequence (QPI Mode) ................................................................................25
Figure 15. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only) .....................................................26
Figure 16. Read Status Register (RDSR) Sequence (SPI Mode) ...............................................................................................28
Figure 17. Read Status Register (RDSR) Sequence (QPI Mode) ...............................................................................................28
Figure 18. Program/Erase flow with read array data
...................................................................................................................29
Figure 19. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
...................................................................30
Figure 20. Write Status Register (WRSR) Sequence (SPI Mode) ..............................................................................................32
Figure 21. Write Status Register (WRSR) Sequence (QPI Mode)..............................................................................................32
Figure 22. WRSR flow
.................................................................................................................................................................34
Figure 23. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ..........................................................................35
Figure 24. Read Data Bytes (READ) Sequence (SPI Mode only) ...............................................................................................36
Figure 25. Read at Higher Speed (FAST_READ) Sequence (SPI Mode) ...................................................................................38
Figure 26. Read at Higher Speed (FAST_READ) Sequence (QPI Mode) ...................................................................................38
Figure 27. Dual Read Mode Sequence (Command 3Bh) ............................................................................................................39
Figure 28. 2 x I/O Read Mode Sequence (SPI Mode only) .........................................................................................................40
Figure 29. Quad Read Mode Sequence (Command 6Bh)...........................................................................................................41
Figure 30. 4 x I/O Read Mode Sequence (SPI Mode) .................................................................................................................43
Figure 31. 4 x I/O Read Mode Sequence (QPI Mode).................................................................................................................43
Figure 32. W4READ (Quad Read with 4 dummy cycles) Sequence ..........................................................................................44
Figure 33. Burst Read - SPI Mode...............................................................................................................................................45
Figure 34. Burst Read - QPI Mode ..............................................................................................................................................45
Figure 35. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode) ............................................................................47
Figure 36. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode) ............................................................................48
Figure 37. Sector Erase (SE) Sequence (SPI Mode) .................................................................................................................49
Figure 38. Sector Erase (SE) Sequence (QPI Mode) .................................................................................................................49
Figure 39. Block Erase 32KB (BE32K) Sequence (SPI Mode)...................................................................................................50
Figure 40. Block Erase 32KB (BE32K) Sequence (QPI Mode) ..................................................................................................50
Figure 41. Block Erase (BE) Sequence (SPI Mode) ....................................................................................................................51
Figure 42. Block Erase (BE) Sequence (QPI Mode) ...................................................................................................................51
Figure 43. Chip Erase (CE) Sequence (SPI Mode) ....................................................................................................................52
Figure 44. Chip Erase (CE) Sequence (QPI Mode)....................................................................................................................52
Figure 45. Page Program (PP) Sequence (SPI Mode) ................................................................................................................54
Figure 46. Page Program (PP) Sequence (QPI Mode) ...............................................................................................................54
Figure 47. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)...........................................................................................55
Figure 48. Deep Power-down (DP) Sequence (SPI Mode) .........................................................................................................56
Figure 49. Deep Power-down (DP) Sequence (QPI Mode) .........................................................................................................56
Figure 50. BP and SRWD if WPSEL=0 .......................................................................................................................................59
Figure 51. WPSEL Flow...............................................................................................................................................................61
Figure 52. Block Lock Flow ..........................................................................................................................................................62
Figure 53. Block Unlock Flow ......................................................................................................................................................63
Figure 54. Suspend to Read Latency ..........................................................................................................................................65
Figure 55. Resume to Suspend Latency .....................................................................................................................................67
Figure 56. Suspend to Program Latency .....................................................................................................................................67
Figure 57. Resume to Read Latency ...........................................................................................................................................68
Figure 58. Software Reset Recovery ...........................................................................................................................................70
Figure 59. Reset Sequence (SPI mode) ......................................................................................................................................70
Figure 60. Reset Sequence (QPI mode) .....................................................................................................................................70
Figure 61. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence ............................................................................71
Figure 62. RESET Timing ............................................................................................................................................................77
Figure 63. Maximum Negative Overshoot Waveform ..................................................................................................................79
Figure 64. Maximum Positive Overshoot Waveform....................................................................................................................79
Figure 65. Input Test Waveforms and Measurement Level .........................................................................................................80
Figure 66. Output Loading ...........................................................................................................................................................80
Figure 67. SCLK TIMING DEFINITION .......................................................................................................................................80
Figure 68. AC Timing at Device Power-Up ..................................................................................................................................84
Figure 69. Power-Down Sequence ..............................................................................................................................................85
Figure 70. Power-up Timing .........................................................................................................................................................86
4
Rev. 1.6, July 12, 2017
P/N: PM1977
MX25U3235F
1.8V 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
•
33,554,432 x 1 bit structure
or 16,777,216 x 2 bits (two I/O mode) structure
or 8,388,608 x 4 bits (four I/O mode) structure
• Equal Sectors with 4K byte each,
or Equal Blocks with 32K byte each
or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program op-
erations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.0V to 1.4V
PERFORMANCE
• High Performance
- Fast read for SPI mode
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 84MHz with 4 dummy cycles,
equivalent to 168MHz
- 4 I/O: 104MHz with 2+4 dummy cycles,
equivalent to 416MHz
- Fast read for QPI mode
- 4 I/O: 84MHz with 2+2 dummy cycles,
equivalent to 336MHz
- 4 I/O: 104MHz with 2+4 dummy cycles,
equivalent to 416MHz
- Fast program time:
0.5ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 12us (typical)
- 8/16/32/64 byte Wrap-Around Burst Read Mode
- Fast erase time:
- 35ms (typ.)/sector (4K-byte per sector);
- 200ms(typ.)/block (32K-byte per block),
- 350ms(typ.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current:
- 20mA(typ.) at 104MHz,
15mA(typ.) at 84MHz
- Low active erase current:
- 18mA(typ.) at Sector Erase, Block Erase
(32KB/64KB);
20mA at Chip Erase
- Low active programming current: 20mA (typ.)
- Standby current: 10uA (typ.)
• Deep Power Down: 1.5uA(typ.)
• Typical 100,000 erase/program cycles
• 20 years data retention
P/N: PM1977
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area
to be software protection against program and erase
instructions
- Additional 4k-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
-
Automatically erases and verifies data at selected
sector or block
-
Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
•
Status Register Feature
•
Command Reset
•
Program/Erase Suspend
•
Electronic Identification
-
JEDEC 1-byte manufacturer ID and 2-byte device
ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and
1-byte device ID
•
Support Serial Flash Discoverable Parameters (SFDP)
mode
HARDWARE FEATURES
•
SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x
I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2
x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or Serial Data Input/Out-
put for 4 x I/O read mode
• RESET#/SIO3
- Hardware Reset pin or Serial input & Output for 4 x
I/O read mode
• PACKAGE
-8-pin SOP (200mil)
-8-land WSON (6x5mm)
-8-land USON (4x3mm)
-8-land XSON(4x4mm)
-12-ball WLCSP
-
All devices are RoHS Compliant and Halogen-
free
5
Rev. 1.6, July 12, 2017
stm32/stm8
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