IDT54/74FCT240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL
BUFFER/LINE DRIVER
IDT54/74FCT240AT/CT
FEATURES:
•
•
•
•
A and C grades
Low input and output leakage
≤
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 64mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
– Industrial: SOIC, SSOP, QSOP
– Military: CERDIP, LCC
DESCRIPTION:
The IDT octal buffer/line driver is built using an advanced dual metal
CMOS technology. The FCT240T is designed to be employed as a memory
and address driver, clock driver, and bus-oriented transmitter/ receiver
which provides improved board density.
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
OE
A
OE
B
DA
0
OB
0
DA
1
OB
1
DA
2
OB
2
DA
3
OB
3
OA
0
DB
0
OA
1
DB
1
OA
2
DB
2
OA
3
DB
3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
© 2009 Integrated Device Technology, Inc.
SEPTEMBER 2009
DSC-5584/8
IDT54/74FCT240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
OE
A
DA
0
OB
0
DA
1
OB
1
DA
2
OB
2
DA
3
OB
3
GND
1
2
3
4
5
6
7
8
9
10
V
CC
OE
B
OA
0
DB
0
OA
1
DB
1
OA
2
DB
2
OA
3
DB
3
DA
1
OB
1
DA
2
OB
2
DA
3
4
5
6
7
8
OE
B
V
CC
20
19
18
17
16
15
14
13
12
11
3 2
20 19
18
1
17
16
15
OE
A
OB
0
DA
0
INDEX
OA
0
DB
0
OA
1
DB
1
OA
2
14
9 10 11 12 1
3
DB
3
D
L
H
X
OB
3
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
PIN DESCRIPTION
Pin Names
OE
A
,
OE
B
Dxx
Ox
x
Inputs
Outputs
Description
3-State Output Enable Inputs (Active LOW)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
FUNCTION TABLE
(1)
OE
A
L
L
H
Inputs
OE
B
L
L
H
Outputs
H
L
Z
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
NOTE:
1. This parameter is measured at characterization but not tested.
2
GND
OA
3
DB
2
IDT54/74FCT240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min, I
IN
= -18mA
—
V
CC
= Max., V
IN
= GND or V
CC
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
µA
V
mV
mA
Unit
V
V
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min
I
OH
= –6mA MIL
I
OH
= –8mA IND
V
IN
= V
IH
or V
IL
I
OH
= –12mA MIL
I
OH
= –15mA IND
V
CC
= Min
I
OL
= 48mA MIL
V
IN
= V
IH
or V
IL
I
OL
= 64mA IND
V
CC
= Max., V
O
= GND
(3)
Min.
2.4
2
—
–60
Typ.
(2)
3.3
3
0.3
–120
Max.
—
—
0.55
–225
V
mA
Unit
V
V
OL
I
OS
Output LOW Voltage
Short Circuit Current
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
3
IDT54/74FCT240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
A
=
OE
B
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE
A
=
OE
B
= GND
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE
A
=
OE
B
= GND
Eight Bits Toggling
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
1.5
3.5
mA
—
1.8
4.5
—
3
6
(5)
—
5
14
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
ΔI
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT240AT
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
Dx to
Ox
Output Enable Time
Output Disable Time
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Ind.
Min.
(2)
Max.
1.5
4.8
1.5
1.5
6.2
5.6
Mil.
Min.
(2)
Max.
1.5
5.1
1.5
1.5
6.5
5.9
FCT240CT
Ind.
Min.
(2)
Max.
1.5
4.3
1.5
1.5
5.8
5.2
Mil.
Min.
(2)
Max.
1.5
4.7
1.5
1.5
6.5
5.7
Unit
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
4
IDT54/74FCT240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
V
CC
500W
V
IN
Pulse
Generator
R
T
D.U.T
.
V
OUT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Switch
Closed
Open
50pF
C
L
500W
All Other Tests
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Octal Link
Test Circuits for All Outputs
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
t
SU
t
H
Pulse Width
Octal Link
Octal Link
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
1.5V
0V
3.5V
1.5V
DISABLE
3V
1.5V
0V
3.5V
0.3V
t
PHZ
0.3V
V
OH
0V
Octal Link
t
PLZ
V
OL
Propagation Delay
Octal Link
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
