DEMO MANUAL DC1975A
LTC2270
16-Bit, 20Msps Dual ADC
Description
Demonstration circuit 1975A supports the
LTC
®
2270
high
speed, high dynamic range ADC. It was specially designed
for applications that require differential DC inputs. DC1975
supports the LTC2270 in CMOS output mode.
The circuitry on the analog inputs is optimized for ana-
log input frequencies from DC to 70MHz. Refer to the
data sheet for proper input networks for different input
frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1975A
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Dc1975 Variants
DC1975 VARIANTS
1975A-A
ADC PART NUMBER
LTC2270
RESOLUTION
16-Bit
MAXIMUM SAMPLE RATE
20Msps
INPUT FREQUENCY
DC to 70MHz
performance summary
PARAMETER
Supply Voltage: DC1975A
Analog Input Range
Logic Input Voltages
Sampling Frequency (Convert Clock
Frequency)
Convert Clock Level
Convert Clock Level
Resolution
Input Frequency Range
CONDITIONS
Specifications are at T
A
= 25°C
MIN
4.5
1
1.3
0.6
1
20
3.6
3.6
16
DC
70
MHz
TYP
MAX
6
2.1
UNITS
V
V
P-P
V
V
Msps
V
V
Depending on Sampling Rate and the A/D Converter
Provided, This Supply Must Provide Up to 300mA
Depending on SENSE Pin Voltage
Minimum Logic High
Maximum Logic Low
Single-Ended Encode Mode (ENC– Tied to GND)
Differential Encode Mode (ENC– Not Tied to GND)
0
0.2
dc1975afa
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DEMO MANUAL DC1975A
Quick start proceDure
DC1975A is easy to set up to evaluate the performance of
the LTC2270 A/D converter. Refer to Figure 1 for proper
measurement equipment setup and follow the procedure
in the Setup section.
SETUP
The DC890 USB demonstration circuit was supplied with
the DC1975 demonstration circuit. Follow the DC890
Quick Start Guide to install the required software and for
connecting the DC890 to the DC1975 and to a PC.
4.5V TO 6V
+
DIFFERENTIAL
ANALOG INPUT
CHANNEL 1
PARALLEL DATA
OUTPUT TO DC890
DIFFERENTIAL
ANALOG INPUT
CHANNEL 2
JUMPERS ARE SHOWN
IN DEFAULT POSITIONS
dc1975 F01
SINGLE-ENDED ENCODE
CLOCK FROM DC1075
Figure 1. DC1975A Setup
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DEMO MANUAL DC1975A
HarDware setup
SMAs:
J1 AIN1+ and J2 AIN1–:
Differential Inputs for Channel 1.
Apply a differential signal to these SMA connectors from
a differential driver. There are 50Ω resistors at the end of
each transmission line that serve as termination for the
differential driver. These SMAs are positioned 0.8" apart
to accommodate LTC differential driver boards.
J3 AIN2+ and J4 AIN2–:
Differential Inputs for Channel 2.
Apply a differential signal to these SMA connectors from
a differential driver. There are 50Ω resistors at the end of
each transmission lines that serve as termination for the
differential driver. These SMAs are positioned 0.8" apart
to accommodate LTC differential driver boards.
J5 ENC+:
Positive Encode Clock Input. As a default the
demo board is populated to accept a single-ended clock
input from a DC1075A demo board, or an equivalent CMOS
signal. For other population options see the Encode Clock
section of this manual.
J6 ENC–:
Negative Encode Clock Input. As a default this
input port is grounded to accommodate the single ended
clock drive. For other population options see the Encode
clock section of this manual.
TURRETS:
V+ (TP5):
Positive Input Voltage for the ADC and Digital
Buffers. This voltage feeds a regulator that supplies the
proper voltages for the ADC and buffers. The voltage range
for this turret is 4.5V up to 6V.
EXT REF (TP1):
Optional Reference Programming Volt-
age. This pin is connected directly to the SENSE pin of
the ADC. If no external voltage is supplied this pin will be
pulled to VDD through a weak pull-up resistor. This will
select the ±1V input range. Connect to GND to select the
±0.5V input range, an external reference between 0.625V
and 1.3V will select an input range of
±0.8 •
V
SENSE
.
GND (TP2, TP6, TP7):
Ground Connection. This demo
board only has a single ground plane. One of these turrets
should be tied to the GND terminal of the power supply
being used. Extra GND pins are available for convenience
when probing.
VCM1 (TP3):
Common-Mode Voltage for Channel 1. This
turret provides the common-mode voltage from the ADC
for channel 1. It is meant to be used to bias the common-
mode bias pin of the differential driver.
VCM2 (TP4):
Common-Mode Voltage for Channel 2. This
turret provides the common-mode voltage from the ADC
for channel 2. It is meant to be used to bias the common-
mode bias pin of the differential driver.
JUMPERS:
The DC1975A demonstration circuit board should have
the following jumper settings as default positions (as per
Figure 1) which configures the ADC in serial programming
mode. In the default configuration JP3-JP6 should be left in
the default locations. This will pull those pins high through
weak pull-up resistors so that the SPI commands can be
sent from the PC. When JP2 is set to PAR, then jumpers
JP3-JP6 can be configured manually.
JP1 WP:
EEPROM Write Protect. For factory use only.
Should be left in the enable (EN) position.
JP2 PAR/SER:
Selects Parallel or Serial Programming
Mode. (Default: serial)
JP3 Duty Cycle Stab:
In parallel programming mode
enables or disables duty cycle stabilizer. In serial program-
ming mode, pull up to VDD. (Default: Enable or pull up)
JP4 SHDN:
In parallel programming mode enables or
disables LTC2270. In serial programming mode, pull up
to VDD. (Default: Enable or pull up)
JP5 NAP:
In parallel programming mode enables or disables
NAP mode. In serial programming mode, pull up to V
DD
.
(Default: Enable or pull up)
JP6 LVDS/CMOS:
In parallel programming mode selects
between LVDS or CMOS output signaling. In serial pro-
gramming mode, pull up to VDD. (Default: LVDS or pull
up). Note: In parallel mode CMOS mode must be selected.
LVDS mode not supported on the DC1975 demo board.
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DEMO MANUAL DC1975A
applying power & signals to tHe Dc1975 Demonstration
circuit
If a DC890 is used to acquire data from the DC1975, the
DC890 must FIRST be connected to a powered USB port
or provided an external 6V to 9V BEFORE applying 4.5V to
6V across the pins marked V+ and GND on the DC1975.
DC1975 requires 4.5V for proper operation. Regulators
on the board produce the voltages required for the ADC.
The DC1975 demonstration circuit requires up to 300mA
depending on the sampling rate and the A/D converter
supplied.
The DC890 data collection board is powered by the USB
cable and does require an external power supply when
collecting data from an LVDS demo board. It must be
supplied an external 6V to 9V on turrets G7(+) and G1(–)
or the adjacent 2.1mm power jack.
analog input network
In the default setup both of the inputs are brought out to
SMA connectors so the demo board can be driven with
a differential source. The DC1975 is populated with no
filtering between the input SMAs and the ADC. There are
provisions for a custom filter to be designed and installed
between the off board driver and ADC.
A common-mode voltage is provided on turrets TP3 and
TP4 that can be used to bias the driver. If the driver is sup-
plying the common-mode voltage R10 and R20 should be
removed, and the common-mode voltage from the driver
can be connected on turrets TP3 and TP4.
In almost all cases, off-board filters will be required on the
analog inputs of the differential driver boards to achieve
data sheet SNR.
The off-board filters should be located close to the inputs
of the differential driver board to avoid reflections from
impedance discontinuities at the driven end of a long
transmission line. Most filters do not present 50Ω outside
the passband. In some cases, 3dB to 10dB pads may be
required to obtain low distortion.
Apply the analog input signal of interest to the SMA
connectors on the DC1975 demonstration circuit board
marked J1-J4.
4
dc1975afa
DEMO MANUAL DC1975A
encoDe clock
Apply an encode clock to the SMA connector on the
DC1975A demonstration circuit board marked J5. As a
default, the DC1975A is populated to have a single-ended
input.
For the best noise performance, the ENCODE INPUT must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator, a squaring circuit
can be used. Linear Technology also provides DC1075A,
a demo board that divides a high frequency sine wave by
four, producing a low jitter square wave for best results
with the LTC2270.
Using a bandpass filter on the clock will improve the noise
performance by reducing the wideband noise power of the
signal. In the case of the DC1975, a bandpass filter used
for the clock should be used prior to the DC1075A. Data
sheet FFT plots are taken with 10 pole LC filters made
by TTE (Los Angeles, CA) to suppress signal generator
harmonics, nonharmonically related spurs and broadband
noise. Low phase noise Agilent 8644B generators are used
with TTE bandpass filters for both the clock input and the
analog inputs.
An internally generated conversion clock output is
available on P1, which could be collected via a logic
analyzer, or other data collection system if populated
with a SAMTEC MEC8-150 type connector or collected
by the DC890 QuikEval™ II data acquisition board using
PScope™ software.
clock network
The clock network on the DC1975 can support a variety of
clock inputs. As a default it is populated to accept a single
ended square wave clock from a DC1075 or appropriate
signal generator. This will drive the ENC+ pin single ended
and the ENC– pin on the ADC is tied to GND.
When using a single-ended sine wave generator to drive
the encode input of the ADC, it is best to use a single-
ended-to-differential translation circuit. To modify the
DC1975 to accommodate this first move the 0Ω resistor
populated in position R26 to position R28, and move R27
and R37 to the R29 and R34 locations. This will direct
the signal through the transformer T1 which will do the
single ended to differential translation.
When using a PECL or LVDS clock you can drive the
DC1975 differentially through J5 and J6. From the default
population, remove the 0ohm resistor in the C32 position
and add the appropriate termination for your clock signal.
R24, R25, R32, R38 and R39 are available to provide the
proper termination for LVDS, PECL, or CML signaling.
Blocking capacitors can be installed in the R30 and R35
positions if the common-mode voltage of the clock is not
compatible with the LTC2270.
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PCB设计
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