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06126D335KAT2A

产品描述CAP CER 3.3UF 6.3V X5R 0612
产品类别无源元件    电容器   
文件大小360KB,共4页
制造商AVX
标准
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06126D335KAT2A概述

CAP CER 3.3UF 6.3V X5R 0612

06126D335KAT2A规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称AVX
包装说明, 0612
Reach Compliance Codecompliant
ECCN代码EAR99
Factory Lead Time9 weeks
电容3.3 µF
电容器类型CERAMIC CAPACITOR
介电材料CERAMIC
高度1.27 mm
JESD-609代码e3
长度1.6 mm
制造商序列号0612
安装特点SURFACE MOUNT
多层Yes
负容差10%
端子数量2
最高工作温度85 °C
最低工作温度-55 °C
封装形状RECTANGULAR PACKAGE
封装形式SMT
包装方法TR, EMBOSSED, 7 INCH
正容差10%
额定(直流)电压(URdc)6.3 V
系列SIZE(LOW INDUCTANCE)
尺寸代码0612
表面贴装YES
温度特性代码X5R
温度系数15% ppm/°C
端子面层Matte Tin (Sn) - with Nickel (Ni) barrier
端子形状WRAPAROUND
宽度3.2 mm

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Low Inductance Capacitors
Introduction
The signal integrity characteristics of a Power Delivery
Network (PDN) are becoming critical aspects of board level
and semiconductor package designs due to higher operating
frequencies, larger power demands, and the ever shrinking
lower and upper voltage limits around low operating voltages.
These power system challenges are coming from mainstream
designs with operating frequencies of 300MHz or greater,
modest ICs with power demand of 15 watts or more, and
operating voltages below 3 volts.
The classic PDN topology is comprised of a series of
capacitor stages. Figure 1 is an example of this architecture
with multiple capacitor stages.
An ideal capacitor can transfer all its stored energy to a load
instantly. A real capacitor has parasitics that prevent
instantaneous transfer of a capacitor’s stored energy. The
true nature of a capacitor can be modeled as an RLC
equivalent circuit. For most simulation purposes, it is possible
to model the characteristics of a real capacitor with one
Slowest Capacitors
capacitor, one resistor, and one inductor. The RLC values in
this model are commonly referred to as equivalent series
capacitance (ESC), equivalent series resistance (ESR), and
equivalent series inductance (ESL).
The ESL of a capacitor determines the speed of energy
transfer to a load. The lower the ESL of a capacitor, the faster
that energy can be transferred to a load. Historically, there
has been a tradeoff between energy storage (capacitance)
and inductance (speed of energy delivery). Low ESL devices
typically have low capacitance. Likewise, higher capacitance
devices typically have higher ESLs. This tradeoff between
ESL (speed of energy delivery) and capacitance (energy
storage) drives the PDN design topology that places the
fastest low ESL capacitors as close to the load as possible.
Low Inductance MLCCs are found on semiconductor
packages and on boards as close as possible to the load.
Fastest Capacitors
Semiconductor Product
VR
Bulk
Board-Level
Package-Level
Die-Level
Low Inductance Decoupling Capacitors
Figure 1 Classic Power Delivery Network (PDN) Architecture
LOW INDUCTANCE CHIP CAPACITORS
The key physical characteristic determining equivalent series
inductance (ESL) of a capacitor is the size of the current loop
it creates. The smaller the current loop, the lower the ESL. A
standard surface mount MLCC is rectangular in shape with
electrical terminations on its shorter sides. A Low Inductance
Chip Capacitor (LICC) sometimes referred to as Reverse
Geometry Capacitor (RGC) has its terminations on the longer
side of its rectangular shape.
When the distance between terminations is reduced, the size
of the current loop is reduced. Since the size of the current
loop is the primary driver of inductance, an 0306 with a
smaller current loop has significantly lower ESL then an 0603.
The reduction in ESL varies by EIA size, however, ESL is
typically reduced 60% or more with an LICC versus a
standard MLCC.
INTERDIGITATED CAPACITORS
The size of a current loop has the greatest impact on the ESL
characteristics of a surface mount capacitor. There is a
secondary method for decreasing the ESL of a capacitor.
This secondary method uses adjacent opposing current
loops to reduce ESL. The InterDigitated Capacitor (IDC)
utilizes both primary and secondary methods of reducing
inductance. The IDC architecture shrinks the distance
between terminations to minimize the current loop size, then
further reduces inductance by creating adjacent opposing
current loops.
An IDC is one single capacitor with an internal structure that
has been optimized for low ESL. Similar to standard MLCC
versus LICCs, the reduction in ESL varies by EIA case size.
Typically, for the same EIA size, an IDC delivers an ESL that
is at least 80% lower than an MLCC.
72
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