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T431616E-7SG: 产品描述1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM; 文件大小772KB，共74页; 制造商TM Technology, Inc.; 官网地址http://www.tmtech.com.tw/

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T431616E-7SG概述

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

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T431616D/E

SDRAM

FEATURES

Fast access time: 5/6/7 ns

•

Fast clock rate: 200/166/143 MHz

•

Self refresh mode: standard and low power

•

Internal pipelined architecture

•

512K word x 16-bit x 2-bank

•

Programmable Mode registers

- CAS# Latency: 1, 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: interleaved or linear burst

- Burst stop function

•

Individual byte controlled by LDQM and UDQM

•

Auto Refresh and Self Refresh

•

4096 refresh cycles/64ms

•

CKE power down mode

•

JEDEC standard +3.3V

0.3V power supply

•

Interface: LVTTL

•

50-pin 400 mil plastic TSOP II package

•

60-ball, 6.4x10.1mm VFBGA package

•

Lead Free Package available for both TSOP II and

VFBGA

•

Low Operating Current for T431616E

1M x 16 SDRAM

512K x 16bit x 2Banks Synchronous DRAM

GRNERAL DESCRIPTION

The T431616D/E SDRAM is a high-speed CMOS

synchronous DRAM containing 16 Mbits. It is internally

configured as a dual 512K word x 16 DRAM with a

synchronous interface (all signals are registered on the

positive edge of the clock signal, CLK). Each of the

512K x 16 bit banks is organized as 2048 rows by 256

columns by 16 bits. Read and write accesses to the

SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of

locations in a programmed sequence. Accesses begin

with the registration of a BankActivate command which

is then followed by a Read or Write command.

The T431616D/E provides for programmable Read

or Write burst lengths of 1, 2, 4, 8, or full page, with a

burst termination option. An auto precharge function

may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst sequence. The

refresh functions, either Auto or Self Refresh are easy to

use. By having a programmable mode register, the

system can choose the most suitable modes to maximize

its performance. These devices are well suited for

applications requiring high memory bandwidth and

particularly well suited to high performance PC

applications

Key Specifications

T431616D/E

CK3

RAS

AC3

Clock Cycle time(min.)

Row Active time(max.)

Access time from CLK(max.)

Row Cycle time(min.)

-5/6/7

5/6/7ns

35/42/42 ns

4.5/5/5.5 ns

48/54/63 ns

ORDERING INFORMATION

Part Number

T431616D-5S/C

T431616D-5SG/CG

T431616D-6S/C

T431616D-6SG/CG

T431616D-7S/C

T431616D-7SG/CG

T431616E-7S/C

T431616E-7SG/CG

G : indicates Lead Free Package

Frequency

200MHz

166MHz

143MHz

Package

TSOP II / VFBGA

TM Technology Inc. reserves the right

P. 1

to change products or specifications without notice.

Publication Date: FEB. 2007

Revision: A

Symbol

CLK

CKE

T431616D/E

Description

Clock:

CLK is driven by the system clock. All SDRAM input signals are sampled on the positive

edge of CLK. CLK also increments the internal burst counter and controls the output registers.

Clock Enable:

CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low

synchronously with clock(set-up and hold time same as other inputs), the internal clock is

suspended from the next clock cycle and the state of output and burst address is frozen as long as

the CKE remains low. When both banks are in the idle state, deactivating the clock controls the

entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device

enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the

same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh

modes, providing low standby power.

Bank Select:

A11(BS) defines to which bank the BankActivate, Read, Write, or BankPrecharge

command is being applied.

Address Inputs:

A0-A10 are sampled during the BankActivate command (row address A0-A10)

and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select

one location out of the 256K available in the respective bank. During a Precharge command, A10

is sampled to determine if both banks are to be precharged (A10 = HIGH). The address inputs also

provide the op-code during a Mode Register Set command.

Chip Select:

CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder.

All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection

on systems with multiple banks. It is considered part of the command code.

Row Address Strobe:

The RAS# signal defines the operation commands in conjunction with the

CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are

asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the

Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the

BankActivate command is selected and the bank designated by BS is turned on to the active state.

When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by

BS is switched to the idle state after the precharge operation.

Column Address Strobe:

The CAS# signal defines the operation commands in conjunction with

the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held

"HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW."

Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."

Write Enable:

The WE# signal defines the operation commands in conjunction with the RAS#

and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the

BankActivate or Precharge command and Read or Write command.

Data Input/Output Mask:

LDQM and UDQM are byte specific, nonpersistent I/O buffer

controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is sampled HIGH.

Input data is masked when LDQM/UDQM is sampled HIGH during a write cycle. Output data is

masked (two-clock latency) when LDQM/UDQM is sampled HIGH during a read cycle. UDQM

masks DQ15-DQ8, and LDQM masks DQ7-DQ0.

The I/Os are byte-maskable during Reads and Writes.

No Connect:

These pins should be left unconnected.

DQ Power:

Provide isolated power to DQs for improved noise immunity. ( 3.3V

0.3V )

DQ Ground:

Provide isolated ground to DQs for improved noise immunity. ( 0 V )

Power Supply:

+3.3V

0.3V

Ground

Pin Descriptions (

Table 1. Pin Details of T431616D/E)

Type

Input

A11

A0-A10

Input

CS#

Input

RAS#

Input

CAS#

Input

WE#

Input

LDQM,

UDQM

Input

DQ0-DQ15

DDQ

SSQ

Input/Output

Data I/O:

The DQ0-15 input and output data are synchronized with the positive edges of CLK.

Supply

TM Technology Inc. reserves the right

P. 4

to change products or specifications without notice.

Publication Date: FEB. 2007

Revision: A

T431616E-7SG相似产品对比

	T431616E-7SG	T431616E-7CG	T431616D-7CG
描述	1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM	1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM	1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

T431616E-7SG

T431616E-7SG概述

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