tm
•
•
•
•
•
TE
CH
T436432B
SDRAM
FEATURES
3.3V power supply
Clock cycle time : 5 / 5.5 / 6 / 7 / 8 / 10 ns
Internal four banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
•
Burst Read Single-bit Write operation
•
DQM for masking
•
Auto refresh and self refresh
•
64ms refresh period (4K cycle)
•
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length :
1 , 2 , 4 , 8 or full page for Sequential Burst
1 , 2 , 4 or 8 for Interleave Burst
•
Available package type :
- 86 pin 400mil TSOP(II) and Lead free
•
Operating temperature :
- 0 ~ +70
°C
2M x 32 SDRAM
512K x 32bit x 4Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T436432B is 67,108,864 bits synchronous
high data rate Dynamic RAM organized as
4 x 524,288 words by 32 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
PART NUMBER EXAMPLES
PART NO.
CLOCK
CYCLE TIME
5ns
5ns
5.5ns
5.5ns
6ns
6ns
7ns
7ns
8ns
8ns
10ns
10ns
MAX
FREQUENCY
PACKAGE
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
OPERATING
TEMPERATURE
T436432B-5SG
T436432B-5S
T436432B-55SG
T436432B-55S
T436432B-6SG
T436432B-6S
T436432B-7SG
T436432B-7S
T436432B-8SG
T436432B-8S
T436432B-10SG
T436432B-10S
200 MHz
200 MHz
183 MHz
183 MHz
166 MHz
166 MHz
143 MHz
143 MHz
125 MHz
125 MHz
100 MHz
100 MHz
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
tm
V
D D
TE
CH
T436432B
PIN ARRANGEMENT
(TSOP-II
Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
V ss
D Q 15
V
SSQ
D Q 0
V
D D Q
D Q 1
D Q 2
V
SSQ
D Q 14
D Q 13
V
D D Q
D Q 3
D Q 4
V
D D Q
D Q 12
D Q 11
V
SSQ
D Q 5
D Q 6
V
SSQ
D Q 10
D Q 9
V
D D Q
D Q 7
N .C
V
D D
8 6 P IN T S O P (II)
(4 0 0 m il)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D Q 8
N .C
V ss
D Q M 1
N .C
N .C
C LK
C K E
A 9
A 8
A 7
A 6
A 5
A 4
A 3
D Q M 3
V
SS
D Q M 0
W E
C A S
R A S
C S
N .C
B S 0
B S 1
A 1 0 /A P
A 0
A 1
A 2
D Q M 2
V
D D
N .C
D Q 16
V
SSQ
N .C
D Q 31
V
D D Q
D Q 17
D Q 18
V
D D Q
D Q 30
D Q 29
V
SSQ
D Q 19
D Q 20
V
SSQ
D Q 28
D Q 27
V
D D Q
D Q 21
D Q 22
V
D D Q
D Q 26
D Q 25
V
SSQ
D Q 23
V
D D
D Q 24
V ss
TM Technology Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
tm
TE
CH
T436432B
BLOCK DIAGRAM
I/O Control
Bank Select
D ata Input R egister
512K x 32
512K x 32
512K x 32
512K x 32
Row Decoder
Row Buffeer
Refresh Counter
Sense AM P
Output Buffer
DQ
Address Register
A DD
C olum n D ecoder
Tim ing Register
Col. Buffer
Latency & Burst Length
Program m ing R egister
C LK
C KE
CS
R AS
C AS
WE
D QM
TM Technology Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
tm
PIN
CLK
TE
CH
T436432B
PIN DESCRIPTION
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CS
CKE
Clock Enable
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
A0 ~ A10/AP
Address
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
Auot-precharge flag : A10/AP
BS0~1
Bank Select Address
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
RAS
Row Address Strobe
with
RAS
low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
CAS
Column Address Strobe
with
CAS
low.
Enables column access .
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C
Write Enable
Data Input/Output
Mask
Data Input/Output
Data Output
Power/Ground
No Connection
Power Supply/Ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
No Connection.
TM Technology Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
tm
BankActivate
BankPrecharge
PrechargeAll
Write
TE
CH
T436432B
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows
the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
CKE
n-1
CKE
n
DQM
(6)
BS
0,1
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
A
10
L
H
L
H
L
H
A
9-0
X
X
Column
address (A0
~ A7)
Column
address (A0
~ A7)
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
Row address
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
OP code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
L
L
H
L
X
H
L
X
H
L
X
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any
(5)
Active
Any
(PowerDown)
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Active
Note:
Active
H
X
H
X
X
X
X
1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
微控制器 MCU
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