Although Belden makes every reasonable effort to ensure their accuracy at the time of this publication, information and specifications described here in are subject to error or omission and to change without
notice, and the listing of such information and specifications does not ensure product availability.
Belden provides the information and specifications herein on an "ASIS" basis, with no representations or warranties, whether express, statutory or implied. In no event will Belden be liable for any damages
(including consequential, indirect, incidental, special, punitive, or exemplary damages) whatsoever, even if Belden has been advised of the possibility of such damages, whether in an action under contract,
negligence or any other theory, arising out of or in connection with the use, or inability to use, the information or specifications described herein.
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at the date of its publication. This information is designed only as a general guide for the safe handling, storage, and any other operation of the product itself or the one that it becomes a part of. The Product
Disclosure is not to be considered a warranty or quality specification. Regulatory information is for guidance purposes only. Product users are responsible for determining the applicability of legislation and
regulations based on their individual usage of the product.
举例：
module design_top(clk, A, B, C, D, E);
endmodule
则
NET "A" LOC = "E2" ;
NET "B" LOC = "E3" | IOSTANDARD = SSTL2_II ;
NET "C" LOC = "B15" ;
NET "D" IOSTANDARD = ......
FPGA/CPLD
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