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SII1161CTU: 产品描述UXGA PANELLINK RECEIVER; 产品类别其他集成电路（IC）消费电路; 文件大小379KB，共46页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

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SII1161CTU概述

UXGA PANELLINK RECEIVER

SII1161CTU规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Lattice(莱迪斯)
包装说明	TFQFP,
Reach Compliance Code	compliant
ECCN代码	EAR99
商用集成电路类型	CONSUMER CIRCUIT
JESD-30 代码	S-PQFP-G100
长度	14 mm
功能数量	1
端子数量	100
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	TFQFP
封装形状	SQUARE
封装形式	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
座面最大高度	1.2 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	14 mm
Base Number Matches	1

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Technology

SiI 1161

PanelLink Receiver

Data Sheet

Document #

SiI-DS-0096-D

SiI

1161 PanelLink Receiver

Data Sheet

TABLE OF CONTENTS

SiI

1161 Pin Diagram ....................................................................................................................1

Functional Description .................................................................................................................2

Electrical Specifications...............................................................................................................3

Absolute Maximum Conditions ................................................................................................................... 3

Normal Operating Conditions ..................................................................................................................... 3

Digital I/O Specifications ............................................................................................................................. 3

General DC Specifications .......................................................................................................................... 4

General AC Specifications .......................................................................................................................... 5

Compatibility Mode Selection Specifications.............................................................................6

SiI

161B (Compatible) Mode DC Specifications ......................................................................................... 6

SiI

161B (Compatible) Mode AC Specifications.......................................................................................... 8

SiI

1161 (Programmable) Mode DC Specifications .................................................................................... 9

SiI

1161 (Programmable) Mode AC Specifications................................................................................... 11

Timing Diagrams.........................................................................................................................15

Pin Descriptions..........................................................................................................................19

Output Pins ............................................................................................................................................... 19

Differential Signal Data Pins ..................................................................................................................... 19

Configuration Pins..................................................................................................................................... 20

Power Management Pins.......................................................................................................................... 20

Power and Ground Pins............................................................................................................................ 21

Feature Information ....................................................................................................................22

HSYNC De-jitter Function ......................................................................................................................... 22

Clock Detect Function............................................................................................................................... 22

OCK_INV Function ................................................................................................................................... 22

C Slave Interface .................................................................................................................................... 23

TFT Panel Data Mapping .......................................................................................................................... 24

Design Recommendations.........................................................................................................31

Differences Between

SiI

161B and

SiI

1161............................................................................................. 31

Using

SiI

1161 in Multiple-Input Applications............................................................................................ 32

Using

SiI

1161 to Replace TI TFP401 ...................................................................................................... 32

Adjusting Equalizer and Bandwidth .......................................................................................................... 33

Voltage Ripple Regulation......................................................................................................................... 34

Decoupling Capacitors.............................................................................................................................. 35

Series Damping Resistors on Outputs...................................................................................................... 36

Receiver Layout ........................................................................................................................................ 37

PCB Ground Planes.................................................................................................................................. 38

Staggered Outputs and Two Pixels per Clock .......................................................................................... 38

Adjusting Output Timings for Loading....................................................................................................... 38

Packaging ....................................................................................................................................39

Thermal Design Options ........................................................................................................................... 39

ePad Enhancement .................................................................................................................................. 39

Dimensions and Marking .......................................................................................................................... 41

Ordering Information ..................................................................................................................41

iii

SiI-DS-0096-D

SiI

1161 PanelLink Receiver

Data Sheet

LIST OF TABLES

Table 1. DC Parametric Specifications ........................................................................................................... 4

Table 2. General AC Specifications ................................................................................................................ 5

Table 3.

SiI

161B Mode DC Specifications ..................................................................................................... 7

Table 4.

SiI

161B Mode AC Specifications ..................................................................................................... 8

Table 5.

SiI

1161 Mode DC Specifications.................................................................................................... 10

Table 6.

SiI

1161 Mode AC Specifications .................................................................................................... 11

Table 7. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=0.................................... 13

Table 8. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=1.................................... 14

Table 9. One Pixel per Clock Mode Data Mapping....................................................................................... 24

Table 10. Two Pixel per Clock Mode Data Mapping..................................................................................... 24

Table 11. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2

Compliant.................. 25

Table 12. Two Pixels per Clock Input/Output TFT Mode .............................................................................. 26

Table 13. 24-bit One Pixel per Clock Input with 24-bit Two Pixels per Clock Output TFT Mode ................. 27

Table 14. 18-bit One Pixel per Clock Input with 18-bit Two Pixels per Clock Output TFT Mode ................. 28

Table 15. Two Pixels per Clock Input with One Pixel per Clock Output TFT Mode ..................................... 29

Table 16. Output Clock Configuration by Typical TFT Panel Application ..................................................... 30

Table 17. New Pin Functions for

SiI

1161 in Programmable Mode .............................................................. 31

Table 18. Internal I

C Registers.................................................................................................................... 33

Table 19: I

C Register Field Definitions ........................................................................................................ 34

Table 20. Recommended Components for 1-2MHz Noise Suppression...................................................... 36

Table 21. Recommended Components for 100-200kHz Noise Suppression on PVCC .............................. 36

LIST OF FIGURES

Figure 1. Functional Block Diagram ............................................................................................................... 2

Figure 2.

SiI

161B Mode Control of Output Pin Drive Strength ...................................................................... 6

Figure 3. Output Loading in

SiI

161B Mode ................................................................................................... 9

Figure 4.

SiI

1161 Mode Control of Output Pin Drive Strength....................................................................... 9

Figure 5. Receiver Output Setup and Hold Times – OCK_INV=0................................................................ 12

Figure 6. Receiver Output Setup and Hold Times – OCK_INV=1................................................................ 13

Figure 7. Digital Output Transition Times ..................................................................................................... 15

Figure 8. Receiver Clock Cycle/High/Low Times ......................................................................................... 15

Figure 9. Channel-to-Channel Skew Timing ................................................................................................ 15

Figure 10. Receiver Clock-to-Output Delay and Duty Cycle Limits ............................................................. 16

Figure 11. Output Signals Disabled Timing from Clock Inactive .................................................................. 16

Figure 12. Wake-Up on Clock Detect .......................................................................................................... 16

Figure 13. Output Signals Disabled Timing from PD# Active ....................................................................... 17

Figure 14. SCDT Timing from DE Inactive or Active .................................................................................... 17

Figure 15. Two Pixels per Clock Staggered Output Timing Diagram ........................................................... 17

Figure 16. I

C Data Valid Delay (driving Read Cycle data) .......................................................................... 18

Figure 17. I

C Reset Timing at Power-Up or Prior to first I

C Acess............................................................ 18

Figure 18. Block Diagram for OCK_INV....................................................................................................... 22

Figure 19. I

C Byte Read.............................................................................................................................. 23

Figure 20. I

C Byte Write .............................................................................................................................. 23

Figure 21. RESET Generation Delay ........................................................................................................... 31

Figure 22. Recommended RESET Circuit.................................................................................................... 32

Figure 23. Voltage Regulation using TL431 ................................................................................................. 34

Figure 24. Voltage Regulation using LM317 ................................................................................................ 35

Figure 25. Decoupling and Bypass Capacitor Placement............................................................................ 35

Figure 26. Decoupling and Bypass Schematic............................................................................................. 36

Figure 27. Receiver Output Series Damping Resistors ............................................................................... 36

Figure 28. General Signal Routing Recommendations................................................................................ 37

Figure 29. Signal Trace Routing Example.................................................................................................... 37

Figure 30. ePad Diagram ............................................................................................................................. 39

Figure 31. Temperature Rise with Frequency and ePad.............................................................................. 40

Figure 32. Package Diagram........................................................................................................................ 41

SiI-DS-0096-D

SII1161CTU相似产品对比

	SII1161CTU	SII1161CT100
描述	UXGA PANELLINK RECEIVER	Consumer Circuit, CMOS, PQFP100, MS-026AED-HD, TQFP-100
是否Rohs认证	符合	不符合
厂商名称	Lattice(莱迪斯)	Lattice(莱迪斯)
包装说明	TFQFP,	HTFQFP,
Reach Compliance Code	compliant	unknow
商用集成电路类型	CONSUMER CIRCUIT	CONSUMER CIRCUIT
JESD-30 代码	S-PQFP-G100	S-PQFP-G100
长度	14 mm	14 mm
功能数量	1	1
端子数量	100	100
最高工作温度	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFQFP	HTFQFP
封装形状	SQUARE	SQUARE
封装形式	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
座面最大高度	1.2 mm	1.2 mm
最大供电电压 (Vsup)	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V
表面贴装	YES	YES
技术	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm
端子位置	QUAD	QUAD
宽度	14 mm	14 mm

SII1161CTU

SII1161CTU概述

SII1161CTU规格参数

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