DEMO MANUAL
DC981A/DC981B
LTC4263
Main Board, Single Port
Autonomous PSE/Daughter Card PSE
Description
Demonstration circuits 981A and 981B feature the
LTC
®
4263
in single port Power over Ethernet (PoE) power
sourcing equipment (PSE) midspan and endpoint solu-
tions. The LTC4263 is an autonomous single-channel PSE
controller for use in IEEE802.3af compliant PoE systems.
It includes an onboard planar power MOSFET, internal
inrush, current limit, and short-circuit control, powered
device (PD) detection and classification circuitry, and
selectable AC or DC disconnect sensing. Onboard control
algorithms provide complete PSE control operation without
the need of a microcontroller. The LTC4263 simplifies PSE
implementation, needing only a single 48V supply and a
small number of passive support components. Other op-
tions shown on the DC981A include legacy PD detection
enable, midspan backoff timer enable, power class enforce
mode, and power management enable. An LED for each
port is driven by the respective LTC4263 to indicate the
state of the port.
Design files for this circuit board are available at
http://www.linear.com/demo/DC981A
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
performance summary
Table 1. Typical DC981, Specifications are at T
A
= 25°C
PARAMETER
Supply Voltage
Midspan Mode Detection Backoff
Detection Range
Set Maximum Allocated Power
Ethernet Powered Pairs Pinout
CONDITION
Voltage for IEEE802.3af Compliance at Port Output
Midspan Enabled, Failed Detection
Valid IEEE802.3af PD Detection
Power Management Enabled, RPM = 12.4kΩ
Endpoint PSE, Alternative A (MDI)
Midspan PSE, Alternative B
VALUE
46V to 57V
3.2s
17kΩ to 29.7kΩ
17W
1/2(+), 3/6(–)
4/5(+), 7/8 (–)
Quick start proceDure
Demonstration circuits 981A and 981B are easy to set
up to evaluate the performance of the LTC4263. Refer to
Figure 1 for proper measurement equipment setup and
follow the procedure below.
1. Place jumpers in the following positions:
JP1
JP2
JP3
JP4
JP5
JP6
EN
EN
DIS
AC
AC
EN
2. Insert daughter card (DC981B) to main board
(DC981A) at polarized connector J3.
3. Apply 48V across VDD48 and VSS.
4. Connect a scope probe at VOUT_MD and VOUT_EP
both referenced to positive rail VDD48.
5. Connect a valid PD to either midspan PSE or
endpoint PSE.
6. Connect a second PD to the open port.
dc981abf
1
DEMO MANUAL
DC981A/DC981B
operating principles
Figure 1. Basic DC981A/DC981B Equipment Setup
dc981abf
2
DEMO MANUAL
DC981A/DC981B
operating principles
The DC981 provides two implementations of a PSE con-
trolled by the LTC4263, a midspan PSE and an endpoint
PSE. A single 48V supply is all that is required to power
the board. This in turn provides power to the midspan PSE
and endpoint PSE outputs. On each solution, an LTC4263
provides detection, classification, power management, safe
power on, port current limit, and disconnect detection.
Midspan PSE
In the midspan solution, a legacy device (router, switch,
etc.) that does not have PoE is connected to MIDSPAN
IN. Data is passed through to MIDSPAN OUT along with
PoE which goes out to a PD. Power is applied directly
to Ethernet pairs 4/5 and 7/8. The LTC4263 circuitry is
located in a small layout area behind the RJ45 connec-
tor and switches power on the negative rail. To show the
different functions of the LTC4263, jumpers allow for the
user to select the options of AC or DC disconnect, legacy
detection, midspan backoff timing, and class enforce-
ment. An LED that shows the status of the port is driven
by a switcher in the LTC4263 to improve efficiency when
VDD5 is provided internally. Push button switch SW1 ties
the shutdown pin to ground to disable the LTC4263 in the
midspan solution.
A PSE implementing alternative B pin out must back off
from detection for at least two seconds after a failed at-
tempt. This is to avoid conflict of detection, for example,
should a potential endpoint PSE and midspan PSE be
connected to the same PD. To enable this feature, set JP2
to DIS. JP2 ties the MIDSPAN pin to VDD5 to enable the
LTC4263 backoff timer or to VSS to disable. A 3.2s delay
occurs after every failed detect cycle unless the result is
open circuit. If held at VSS, no delay occurs after failed
detect cycles.
Endpoint PSE
The endpoint solution is primarily shown on a small
daughter card (DC981B). This card is the same height
and width as the integrated RJ45 connector that it slides
behind on the main board (DC981A). The RJ45 includes
Ethernet magnetics and common mode termination. A
layout option shows the same components can be placed
under the same RJ45 connector. The minimum connections
to the daughter card are VSS, VDD48 and VOUT. Power is
switched over from the daughter card out to the Ethernet
data pairs (1/2 and 3/6). A PHY can be connected to the
TO PHY
connector to pass data through to the data pairs
along with PoE. LED drive and power management pins
are also brought out for additional board functions. The
board is set up for AC disconnect, but can be reworked
for DC disconnect by removing components and replac-
ing with shorts in certain locations. Two solder jumpers
also provide selectable options for legacy detection and
class enforce.
Power Management
The midspan and endpoint PSEs, although separate solu-
tions on the DC981, are tied together at the PWRMGT pin
for demonstration of the LTC4263 power management
capability. Programmable onboard power management
circuitry allows multiple LTC4263s to allocate and share
power in multiport systems, allowing maximum utilization
of the 48V power supply – all without the intervention of
a host processor.
The LTC4263 sources current (IPM) at the PWRMGT pin
proportional to the class of the PD that it is powering. The
voltage of this pin (VPM) is checked before powering the
port (Table 2). The port will not turn on if this pin is more
than 1V above VSS. The PWRMGT pins of the LTC4263s
are tied together and connect to a resistor (RPM) and
capacitor (CPM) in parallel to VSS to implement power
management. This resistor is selected with the following
equation:
R
PM
= 213kΩ
•
W/P
FULL_LOAD
On the DC981A, the default RPM is 12.4kΩ for a full load
power of 17W.
Table 2. Power Management Voltage
PD CLASS
Class 1
Class 2
Class 0, 3, or 4
*RPM = 12.4kΩ
POWER
REQUEST
4W
7W
15.4W
IPM (TYP)
19μA
33μA
73μA
VPM*
236mV
409mV
905mV
dc981abf
3
DEMO MANUAL
DC981A/DC981B
operating principles
Table 3. Powered Device Combinations
PD COMBINATION
Class 1 / Class 1
Class 1 / Class 2
Class 1 / Class 3**
Class 2 / Class 2
Class 2 / Class 3**
Class 3 **/ Class 3**
1ST PD
Powered
Powered
Powered
Powered
Powered
Powered
2ND PD
Powered
Powered
Power Denied
Powered
Power Denied
Power Denied
VDD5 Option
The logic 5V power supply can be supplied from the internal
LTC4263 5V supply or an external 5V supply when above
the internal supply. If the internal regulator is used, this
pin should only be connected to the bypass capacitor and
to logic pins of the LTC4263 held at VDD5.
AC and DC Disconnect
AC and DC disconnect are two different methods of detect-
ing whether a valid PD is present and requires power. AC
disconnect is the default method for the DC981 but can
be converted to DC disconnect in the midspan solution
through two jumpers. Moving DISCON (JP4) to DC will
short the ACCOUT pin to VSS and configure the LTC4263 to
DC disconnect. Moving jumper setting for ACCOMP (JP5)
to DC bypasses the AC blocking diode and removes the
RC used for AC disconnect from the main circuit.
Legacy Detection
LEGACY jumper JP3 controls whether legacy detect is
enabled. If the LEGACY pin is held at VDD5 (EN selected),
legacy detect is enabled and testing for a large capacitor
is performed to detect the presence of a legacy PD on
the port. If held at VSS (DIS selected), only IEEE 802.3af
compliant PDs are detected. If left floating (no jumper),
the LTC4263 enters force-power-on mode and any PD that
generates between 1V and 10V when biased with 270μA of
detection current will be powered as a legacy device. This
mode is useful if the system uses a differential detection
scheme to detect legacy devices. Warning: Legacy modes
are not IEEE 802.3af compliant.
**Class 3 substitutable with Class 0 or 4.
If power management is not used, move JP6 to DIS to tie
the PWRMGT pins to VSS and disable this feature.
Class Enforce Mode
ENFORCE CLASS jumper JP1 ties the ENFCLS pin of the
LTC4263 to either VDD5 or VSS to respectively enable or
disable class enforce current limits. If held at VDD5, the
LTC4263 will reduce the ICUT threshold for Class 1 or
Class 2 PDs. If ENFCLS is held at VSS, ICUT remains at
375mA (typical) for all classes.
Table 4. Port Current Limit According to Class
PD CLASS
Class 1
Class 2
Class 0, 3, 4, or Class
Enforce Disabled
CURRENT THRESHOLD (TYPICAL)
100mA
175mA
375mA
LED Drive
An LED pin indicates the state of the port controlled by
the LTC4263. When the port is powered, the LED is on;
when disconnected or detecting, the LED is off. If an
invalid signature is detected or a fault occurs, the LED
will flash a pattern that the user or host system can read
to indicate the nature of the problem. When run from a
single 48V supply, the LED pin can operate as a simple
switching current source to reduce power dissipation in
the LED drive circuitry.
dc981abf
4
DEMO MANUAL
DC981A/DC981B
operating principles
Figure 2. DC981 Options
dc981abf
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
