IR3084
XPHASE
DESCRIPTION
The IR3084 Control IC combined with an IR
XPhase
TM
Phase IC provides a full featured and flexible
way to implement a complete VR10 or VR11 power solution. The “Control” IC provides overall system
control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a
multiphase converter. The XPhase
TM
architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
TM
DATA SHEET
VR 10/11 CONTROL IC
FEATURES
1 to X phase operation with matching Phase IC
Supports both VR11 8-bit VID code and extended VR10 7-bit VID code
0.5% Overall System Setpoint Accuracy
VID Select pin sets the DAC to either VR10 or VR11
VID Select pin selects either VR11 or legacy VR10 type startups
Programmable VID offset and Load Line output impedance
Programmable VID offset function at the Error Amp’s non-inverting input allowing zero offset
Programmable Dynamic VID Slew Rate
±300mV Differential Remote Sense
Programmable 150kHz to 1MHz oscillator
Enable Input with 0.85V threshold and 100mV of hysteresis
VR Ready output provides indication of proper operation and avoids false triggering
Phase IC Gate Driver Bias Regulator / VRHOT Comparator
Operates from 12V input with 9.9V Under-Voltage Lockout
6.9V/6mA Bias Regulator provides System Reference Voltage
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Small thermally enhanced 5mm x 5mm, 28 pin MLPQ package
TYPICAL APPLICATION CIRCUIT
CCP1
100pF
EA
RT2
R117
4.7K, B=4450 1.21K
+5.0V
RCP
2.49K
CCP
56nF
R137
2K
18
17
C1009
100pF
VSS_SENSE
RDRP
787
RFB
324
FB
EAOUT VRRDY
IIN
RMPOUT
VBIAS
27
15
19
20
C134
0.1uF
C89
100pF
VR_RDY
ISHARE
RMP
VBIAS
C204
0.1uF
C135
1uF
VREG_12V_FILTERED
R1331
1
Q4
CJD200
VGDRIVE
RFB1
162
VCC_SENSE
CFB
10nF
IR3084MTR
16
OUTEN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID_SEL
VREG_12V_FILTERED
R30
10
28
9
8
7
6
5
4
3
2
1
21
C130
0.1uF
26
CSS/DEL
0.1uF
VOSNS--
10
24
23
25
VDRP
ENABLE
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VIDSEL
VCC
SS/DEL
REGDRV
REGFB
REGSET
RVSETPT
124
VSETPT
OCSET
VDAC
ROSC
LGND
14
13
12
11
22
ROSC 30.1K
ROCSET
15.8K
RVGDRV
97.6K
CVGDRV
10nF
VDAC
RVDAC
3.5
CVDAC
33nF
Page 1 of 45
03/4/2009
IR3084
ORDERING INFORAMATION
DEVICE
IR3084MTRPBF
IR3084MPBF
ORDER QUANTITY
3000 Tape and Reel
100 Piece Strip
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature……………..0 to 150
o
C
Storage Temperature Range………………….−65
o
C to 150
o
C
ESD Rating………………………………………HBM Class 1B JEDEC standard
Moisture Sensitivity Level………………………JEDEC Level 3 @ 260
o
C
PIN #
1
2−9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
VIDSEL
VID7−0
VOSNS−
ROSC
VDAC
OCSET
VSETPT
IIN
VDRP
FB
EAOUT
RMPOUT
VBIAS
VCC
LGND
REGFB
REGDRV
REGSET
SS/DEL
VRRDY
ENABLE
V
MAX
20V
20V
0.5V
20V
20V
20V
20V
20V
20V
20V
10V
20V
20V
20V
n/a
20V
20V
20V
20V
20V
20V
V
MIN
−0.3V
−0.3V
−0.5V
−0.5V
−0.3V
−0.3V
−0.3V
−0.3V
−0.3V
−0.3V
−0.3V
−0.3V
−0.3V
−0.3V
n/a
−0.3V
−0.3V
−0.3V
−0.3V
−0.3V
−0.3V
I
SOURCE
1mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
5mA
1mA
20mA
5mA
50mA
1mA
50mA
1mA
10mA
1mA
1mA
1mA
1mA
I
SINK
1mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
5mA
1mA
20mA
5mA
10mA
50mA
1mA
1mA
50mA
1mA
1mA
20mA
1mA
Page 2 of 45
03/4/2009
IR3084
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 9.5V
≤
V
CC
≤
16V,
−0.3V ≤
VOSNS−
≤
0.3V,
0
o
C
≤
T
J
≤
100
o
C, ROSC = 24kΩ, CSS/DEL = 0.1F ±10%
PARAMETER
VDAC REFERENCE
TEST CONDITION
VID
≥
1V, 10kΩ≤ROSC≤100kΩ,
25
o
C
≤
T
J
≤
100
o
C
0.8V
≤
VID < 1V, 10kΩ≤ROSC≤100kΩ,
25
o
C
≤
T
J
≤
100
o
C
0.5V≤VID<0.8V, 10kΩ≤ROSC≤100kΩ,
25
o
C
≤
T
J
≤
100
o
C
Includes OCSET and VSETPT currents
Includes OCSET and VSETPT currents
0V
≤
VIDx
≤
VCC
Measure Time till VRRDY drives low,
Note 1
VIDSEL FLOATING
MIN
TYP
MAX
UNIT
System Set-Point Accuracy
(Deviation from Tables 1 & 2
per test circuit in Figure 1
which emulates in-VR
operation)
Source Current
Sink Current
VIDx Input Threshold
VIDx & VIDSEL Input Bias
Current
VIDx 11111x Blanking Delay
VIDSEL Pull-up Voltage
VIDSEL Pull-up Resistance
VIDSEL VR10/VR11
Threshold
VIDSEL VR11 No Boot
Threshold
VIDSEL VR10 No Boot
Threshold
ERROR AMPLIFIER
Input Offset Voltage
FB Bias Current
VSETPT Bias Current
DC Gain
Gain Bandwidth Product
Corner Frequency
Slew Rate
Source Current
Sink Current
Max Voltage
Min Voltage
VDRP BUFFER AMPLIFIER
Input Offset Voltage
Source Current
Sink Current
Bandwidth (−3dB)
Slew Rate
Page 3 of 45
−0.5
−5
−8
104
92
500
−5
0.5
1.15
5.0
0.55
3.0
7.0
113
100
600
0
1.3
1.25
12.5
0.62
3.5
7.5
0.5
+5
+8
122
108
700
5
2.1
1.35
20.0
0.69
4.0
8.0
%
mV
mV
μA
A
mV
A
s
V
KΩ
V
V
V
Measure V(FB) – V(VSETPT) per test
circuit in Figure 1. Applies to TBS VID
codes. Note 2.
−5
−1
48.5
90
6
1.4
−1.2
0.5
150
30
−10
−9
0.2
1
5
0.0
−0.3
51
100
10
200
3.2
−0.8
1.0
375
110
−1
−7.3
0.88
6
10
5
0.5
53.5
110
400
5
−0.35
1.7
600
200
6
−4
4.1
mV
A
A
dB
MHz
Hz
V/s
mA
mA
mV
mV
mV
mA
mA
MHz
V/s
Note 1
Note 1
45 deg Phase Shift, Note 1
Note 1
VBIAS–VEAOUT (ref. to VBIAS)
Normal operation or Fault mode
V(VDRP) – V(IIN), 0.5V
≤
V(IIN)
≤
5V
0.5V
≤
V(IIN)
≤
5V
0.5V
≤
V(IIN)
≤
5V
Note 1
Note 1
03/4/2009
IR3084
PARAMETER
CURRENT SENSE INPUT
IIN Bias Current
IIN Preconditioning Pull-Down
Resistance
IIN Preconditioning RESET
Threshold
IIN Preconditioning SET
Threshold
VBIAS REGULATOR
Output Voltage
Current Limit
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
SOFT START AND DELAY
Start Delay (TD1)
Soft Start Time (TD2)
VID Sample Delay (TD3)
VRRDY Delay (TD4 + TD5)
OC Delay Time
SS/DEL to FB Input Offset
Voltage
SS/DEL Charge Current
SS/DEL Discharge Current
Charge/Discharge Current
Ratio
OC Discharge Current
Charge Voltage
OC/VRRDY Delay
Comparator Threshold
OC/VRRDY Delay
Comparator Threshold
Delay Comparator Hysteresis
VID Sample Delay
Comparator Threshold
SS/DEL Discharge
Comparator Threshold
ENABLE INPUT
Threshold Voltage
Threshold Voltage
Threshold Hysteresis
Input Resistance
Blanking Time
ENABLE rising
ENABLE falling
775
675
60
50
75
850
750
100
100
250
925
825
140
200
400
mV
mV
mV
KΩ
ns
RDRP =
∞
RDRP =
∞
1.2
0.8
0.2
0.5
150
0.85
40
4
9.5
Note 1
Relative to Charge Voltage,
SS/DEL rising
Relative to Charge Voltage,
SS/DEL falling
20
3.6
1.8
1.6
1.0
1.3
250
1.3
70
6.5
11.2
40
3.85
80
100
20
3.10
215
2.6
2.8
2.5
2.2
350
1.5
100
9
12.5
60
4.1
ms
ms
ms
ms
µs
V
A
A
A/A
A
V
mV
mV
mV
V
mV
1V
≤
V(OCSET)
≤
5V
−10
−53.5
−1
−51
10
−48.5
mV
A
−5mA ≤
I(VBIAS)
≤
0mA
6.6
−35
6.9
−20
7.2
−6
V
mA
V(SS/DEL) > 0.85V, V(EAOUT) > 0.5V
V(SS/DEL) < 0.35V
V(EAOUT)
V(SS/DEL)
−2.0
5.6
0.20
0.35
−0.2
12.5
0.35
0.60
1.0
19.4
0.50
0.85
A
KΩ
V
V
TEST CONDITION
MIN
TYP
MAX
UNIT
Note 1
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
Noise Pulse < 250ns will not register
an ENABLE state change. Note 1
Page 4 of 45
03/4/2009
IR3084
PARAMETER
VRRDY OUTPUT
Output Voltage
Leakage Current
OSCILLATOR
Switching Frequency
Peak Voltage (4.8V typical,
measured as % of VBIAS)
Valley Voltage (0.9V typical,
measured as % of VBIAS)
DRIVER BIAS REGULATOR
REGSET Bias Current
Input Offset Voltage
Short Circuit Current
Dropout Voltage
Start Threshold
Stop Threshold
Hysteresis
GENERAL
VCC Supply Current
VOSNS− Current
−0.3V ≤
VOSNS−
≤
0.3V,
All VID Codes
9
−1.45
14
−1.3
18
−0.75
mA
mA
1.5V
≤
V(REGSET)
≤
VCC – 1.5V
1.5V
≤
V(REGSET)
≤
VCC – 1.5V,
100A
≤
I(REGDRV)
≤
10mA
V(REGDRV) = 0V,
1.5V
≤
V(REGSET)
≤
VCC – 1.5V,
Note 1
I(REGDRV) = 10mA, Note 1
−112
−12
10
0.4
9.3
8.5
575
−99
0
20
0.87
9.9
9.1
800
−85
12
50
1.33
10.3
9.5
1000
A
mV
mA
V
V
V
mV
450
70
10
500
72
13
550
74
15
kHz
%
%
I(VRRDY) = 4mA
V(VRRDY) = 5.5V
150
0
300
10
mV
A
TEST CONDITION
MIN
TYP
MAX
UNIT
VCC UNDER−VOLTAGE LOCKOUT
Start – Stop
Note 1:
Guaranteed by design but not tested in production
Note 2:
VDAC Output is trimmed to compensate for Error Amp input offsets errors
200 OHM
+
+
"FAST"
VDAC
ISOURCE
ISINK
-
-
VDAC
BUFFER
AMP
IOFFSET
IROSC
Figure 1 – System Set Point Test Circuit
Page 5 of 45
03/4/2009
+
-
CURRENT
SOURCE
GENERATOR
ROSC
BUFFER
AMP
-
IR3084
EAOUT
ERROR
AMP
FB
200 OHM
+
VSETPT
OCSET
VDAC
IROSC
IOCSET
RVDAC
SYSTEM
SET POINT
VOLTAGE
CVDAC
ROSC
+
ROSC
1.2V
-
VOSNS-
嵌入式系统
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